Chapter 4
27
switch back to it when desired. When used with the shadow bank 0 / 1 bit, a double
buffer mechanism is achieved (as described below).
The shadow bank 0 / 1 bit is used to select which half of the 32K RAM fitted onboard
the SPECTRA interface will shadow the Spectrum’s lower 16K RAM. When used with
the display bank 0 / 1 bit, a double buffer mechanism is achieved which allows a
program to be constructing a screen image in the shadow bank while the SPECTRA
interface is outputting the screen information from the display bank. Once construction
of the image has been completed, the roles of the shadow and display banks can be
swapped over, thereby producing an instantaneous update on the television without
any flicker.
The full / half cell bit selects between attributes of 8 pixels wide and 4 pixels wide.
The colour byte(s) read in for a cell (as defined by the single / double byte colour bit)
are interpreted differently for half cell mode than they are for full cell mode. The state of
the basic / extra colours bit determines whether the basic palette of 15 colours or
larger palette of 64 colours is used.
Writing to the display mode register causes an immediate switch to the new
configuration. This can result in a visible flicker should the change occur midway
through a TV frame. Therefore, it may be desirable to wait until an interrupt occurs
before switching to the new mode since this ensures that the change happens prior to
the top border being generated. The immediate switch of display modes opens up the
possibility to force the construction of a hybrid screen by timing the exact moment that
transitions occur between modes.
Note that the standard display mode is always reverted to whenever the reset button is
pressed or when configuration switch 6 is set to the off position. When either condition
happens, the display mode register is loaded with a value of $00 thereby selecting
configuration: row mode, display bank 0, shadow bank 0, standard border, basic
colours, single byte colour and full cell mode.
Display memory organisation
The standard Spectrum screen memory has the pixel display file located at addresses
$4000 to $57FF, and the attributes file located at addresses $5800 to $5AFF. The
ordering of the lines within the display file does not follow a logical progression down
the screen but instead follows the distinctive sequence often seen when a loading
screen is being read in from cassette. This sequence splits the display into 3 areas of
8 rows, with each area ordered by the pixel line positions within the rows. In contrast,
the attributes file is ordered in a logical progression starting from the top row. To
understand why the display file uses such an apparently odd layout requires an
examination of how each memory location within it is addressed. The diagram that
follows shows the addressing schemes for the standard display and attribute files.
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