Sony HCD-DP700 - Page 57

57
HCD-DP700
FunctionPin NamePin No. I/O
58 MOD0 I Operation mode signal input (L : single chip mode, H : use prohibited)
59 EXLOCK I Lock signal input
60 VDDI — Power supply
61 VSS — Ground
62 - 66 A17 - A13 O External memory address output (SRAM)
67 GP10 I/O LRCK0
68 GP9 (DECODE) O DECODE
69 GP8 (AUDIO) I AUDIO
70 VDDI — Power supply
71 VSS — Ground
72 - 75 D15/GP7 - D12/GP4 I/O External memory data input /output (general port)
76 VDDE — Power supply
77 - 80 D11/GP3 - D8/GP0 I/O External memory data input /output (general port)
81 VSS — Ground
82 - 85 A9 - A12 O External memory address output (SRAM)
86 TDO O Simple emulation data output
87 TMS I Simple emulation data input start, end terminal
88 XTRST I Simple emulation async BREAK signal input terminal
89 TCK I Simple emulation clock signal input
90 TDI I Simple emulation data input
91 VSS — Ground
92 - 97 A8 - A3 O External memory address output (SRAM)
98, 99 D7, D6 I/O External memory data input/output (SRAM)
100 VDDI — Power supply
101 VSS — Ground
102 - 105 D5 - D2 I/O External memory data input/output (SRAM)
106 VDDE — Power supply
107, 108 D1, D0 I/O External memory data input/output (SRAM)
109, 110 A2, A1 O External memory address output (SRAM)
111 VSS — Ground
112 A0 O External memory address output (SRAM)
113 PM I PLL initialization input terminal
114, 115 SDI3, SDI4 I Audio IF data input
116 SYNC I Sync/async selection input (L : sync, H : async)
117 - 119 VSS — Ground
120 VDDI — Power supply