PCM-D50
18
SECTION 4
DIAGRAMS
For Schematic Diagrams.
Note:
• All capacitors are in F unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in and
1
/4 W or less unless otherwise
specifi ed.
•
º
: internal component.
• Ý : panel designation.
THIS NOTE IS COMMON FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is printed in each block.)
• ß : B+ Line.
• Þ : B– Line.
• Power voltage is dc 6.0V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark
: PB
[ ] : REC
ö
: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 M ).
Voltage variations may be noted due to normal production
tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal production
tolerances.
• Circled numbers refer to waveforms.
• Signal path.
½ : REC (DIGITAL)
Ô : REC (ANALOG)
Ö : PB (DIGITAL)
Ú : PB (ANALOG)
For Printed Wiring Boards.
Note:
• È : Parts extracted from the component side.
• : Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side:
(SIDE B)
Parts face side:
(SIDE A)
Parts on the pattern face side seen from
the pattern face are indicated.
Parts on the parts face side seen from
the parts face are indicated.
Note:
The components identi-
fi ed by mark ð or dotted
line with mark ð are criti-
cal for safety.
Replace only with part
number specifi ed.
Note:
Les composants identifi és
par une marque ð sont
critiques pour la sécurité.
Ne les remplacer que par
une piéce portant le nu-
méro spécifi é.
• Lead layouts
surface
CSP (Chip Size Package) Lead layout of conventional IC
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
from that of conventional IC.
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