Sony STR-D2010 - Page 34

STR-D2010 |
IC506, IC507 Digital - Audio Signal Processing LSIs CXD1160P
These are digital audio signal processing LSIs which incorporate instruction RAM, coefficient
RAM, data RAM, multiplier and level shifter and are equipped with serial I/O, delay I/O (max.
capability: stereo 1024 sampling + delay) and microcomputer interface for peripheral devices.
Pin No. Symbol [ov oO Description
1 SDT I Serial + data input terminal to receive instructions, coefficients,
I/O controls transferred from the microcomputer.
SCK I SDT serial * clock input terminal to fetches in data at a rise.
3 XSLD I Input terminal for a latch signal from the system mi-
crocomputer to latch serial * data inside the IC. LOW active
(LCK for DPAC1).
4 S]O2 I Input terminal to set the number of serial bit clocks BCK in
each channels (chl or ch2) data transfer in one sampling sec-
tion. 32-bit clock mode when fixed at GND, and 24-bit clock
mode when fixed at +5V. (32 bits for this set)
5 DYSL I Delay I/O mode selector input terminal. Serial mode when
fixed at GND, and similar operation to serial I/O. Delay mode
when fixed at +5V, and a delay line equivalent to 2-channels
is configured by connecting to external DRAM (64kbits).
6 TST I Test pin. Normally, fix at GND.
7 VSS GND terminal.
8 MCK1 I Master clock input 1. The master clock ACK inside the IC is
half this frequency. Fix MCK2 at +5V when inputting the
master clock from MCK2.
9 MCK2 I Master clock input 2. The master clock ACK inside the IC is
the same frequency as this. Fix MCK1 at +5V or GND when
inputting the master clock from MCK 2.
10 SI I l-sampling 2-channel serial data input terminal.
ll SO oO l-sampling 2-channel serial data output terminal.
12 BCK I Serial bit clock input terminal for SI and SO. Serial input data
is fetched in at a rise of this BCK and output data is sent out.
(64FS)
13 LRCK I FS clock input terminal for I/O (1FS)
14 XOVF O Adder/subtracter overflow detection output. “L” at overflow
time.
15 A6 O External DRAM address output A6
16 A3 O External DRAM address output A3
17 A4 oO External DRAM address output A4
18 AS O External DRAM address output A5
19 AZ7 oO External DRAM address output A7
20 XCLR I Test pin. Normally, fix at +5V.
21 VDD => +5V power supply terminal.
22 Al O External DRAM address output Al
23 A2 O External DRAM address output A2
24 AO O External DRAM address output A0
25 XRAS O Low address « strobe output terminal for external DRAM.
26 XWSO oO Serves as a seria! data output terminal when DYSL is at “L”,
and works in accordance with each serial I/O mode. Serves as
an external DRAM write enable output terminal when DYSL
is at “H”.
27 DIO 1/0 Serves as a serial data input terminal when DYSL is at “L”,
and fetches in data ds accordance with each serial I/O mode.
When DYSL is at “H”, it serves as an external DRAM data
input/output terminal to be used as a common line for data
input D;, and data output Doyr.
L 28 XCAS O —tt Column address strobe output terminal for external DRAM.