Advanced-control timers (TIM1/TIM8/TIM20) RM0440
1216/2126 RM0440 Rev 4
28.6.26 TIMx timer input selection register (TIMx_TISEL)(x = 1, 8, 20)
Address offset: 0x05C
Reset value: 0x0000 0000
Bits 4:3 Reserved, must be kept at reset value.
Bits 2:1 IDIR[1:0]: Index direction
This bit indicates in which direction the Index event resets the counter.
00: Index resets the counter whatever the direction
01: Index resets the counter when up-counting only
10: Index resets the counter when down-counting only
11: Reserved
Note: The IDR[1:0] bitfield must be written when IE bit is reset (index disabled).
Bit 0 IE: Index enable
This bit indicates if the Index event resets the counter.
0: Index disabled
1: Index enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. TI4SEL[3:0] Res. Res. Res. Res. TI3SEL[3:0]
rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. TI2SEL[3:0] Res. Res. Res. Res. TI1SEL[3:0]
rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 TI4SEL[3:0]: Selects tim_ti4[0..15] input
0000: tim_ti4_in0: TIMx_CH4
0001: tim_ti4_in1
...
1111: tim_ti4_in15
Refer to Section 28.3.2: TIM1/TIM8/TIM20 pins and internal signals for interconnects list.
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 TI3SEL[3:0]: Selects tim_ti3[0..15] input
0000: tim_ti3_in0: TIMx_CH2
0001: tim_ti3_in1
...
1111: tim_ti3_in15
Refer to Section 28.3.2: TIM1/TIM8/TIM20 pins and internal signals for interconnects list.
Bits 15:12 Reserved, must be kept at reset value.
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