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General-purpose timers (TIM15/TIM16/TIM17) RM0440

1418/2126 RM0440 Rev 4

30.7.23 TIM15 register map

TIM15 registers are mapped as 16-bit addressable registers as described in the table

below:

Bits 31:0 DMAB[31:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address

(TIM15_CR1 address) + (DBA + DMA index) x 4

where TIM15_CR1 address is the address of the control register 1, DBA is the DMA base

address configured in TIM15_DCR register, DMA index is automatically controlled by the

DMA transfer, and ranges from 0 to DBL (DBL configured in TIM15_DCR).

Table 300. TIM15 register map and reset values

Offset

name

0x00

TIM15_CR1

Res.

UIFREMA

Res.

CKD

[1:0]

ARPE

Res.

OPM

URS

UDIS

CEN

Reset value 0000 0000

0x04

TIM15_CR2

Res.

OIS2

OIS1N

OIS1

TI1S

MMS[2:0]

CCDS

CCUS

Res.

CCPC

Reset value 000000000 0

0x08

TIM15_SMCR

Res.

[4:3]

Res.

SMS[3]

Res.

MSM

TS[2:0]

Res.

SMS[2:0]

Reset value 0 0 0 0 0 0 0 0 0 0

0x0C

TIM15_DIER

Res.

TDE

COMDE

Res.

CC2DE

CC1DE

UDE

BIE

TIE

COMIE

Res.

CC2IE

CC1IE

UIE

Reset value 0 0 0 0 0 0 0 0 0 0 0

0x10

TIM15_SR

Res.

CC2OF

CC1OF

Res.

BIF

TIF

COMIF

Res.

CC2IF

CC1IF

UIF

Reset value 00 000 000

0x14

TIM15_EGR

Res.

COMG

Res.

CC2G

CC1G

Reset value 000 000

0x18

TIM15_CCMR1

Input Capture

mode

Res.

IC2F[3:0]

IC2

PSC

[1:0]

CC2S

[1:0]

IC1F[3:0]

IC1

PSC

[1:0]

CC1S

[1:0]

Reset value 0000000 000 000000

TIM15_CCMR1

Output

Compare mode

Res.

OC2M[3]

Res.

OC1M[3]

OC2CE

OC2M

[2:0]

OC2PE

OC2FE

CC2S

[1:0]

OC1CE

OC1M

[2:0]

OC1PE

OC1FE

CC1S

[1:0]

Reset value 0 00000000 0000 0000 0

Brand	ST
Model	STM32G491
Category	Microcontrollers
Language	English

ST STM32G491 User Manual

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