High-resolution timer (HRTIM) RM0440
906/2126 RM0440 Rev 4
Table 226 lists the registers which can be preloaded, together with a summary of available
update events.
The master timer has 4 update options:
1. Software: writing 1 into MSWU bit in HRTIM_CR2 forces an immediate update of the
registers. In this case, any pending hardware update request is cancelled.
2. Update done when the master counter rolls over and the master repetition counter is
equal to 0. This is enabled when MREPU bit is set in HRTIM_MCR.
3. Update done once burst DMA is completed (see Section 27.3.23 for details). This is
enabled when BRSTDMA[1:0] = 01 in HRTIM_MCR. It is possible to have both
MREPU=1 and BRSTDMA=01.
Note: The update can take place immediately after the end of the burst sequence if
SWU bit is set (i.e. forced update mode). If SWU bit is reset, the update is done on the
next update event following the end of the burst sequence.
4. Update done when the master counter rolls over following a burst DMA completion.
This is enabled when BRSTDMA[1:0] = 10 in HRTIM_MCR.
An interrupt or a DMA request can be generated by the master update event.
Table 226. HRTIM preloadable control registers and associated update sources
Timer Preloadable registers Preload enable Update sources
Master timer
HRTIM_DIER
HRTIM_MPER
HRTIM_MREP
HRTIM_MCMP1R
HRTIM_MCMP2R
HRTIM_MCMP3R
HRTIM_MCMP4R
PREEN bit in
HRTIM_MCR
Software
Repetition event
Burst DMA event
Repetition event following a burst
DMA event
Timer x
x = A..F
HRTIM_TIMxDIER
HRTIM_TIMxPER
HRTIM_TIMxREP
HRTIM_TIMxCMP1R
HRTIM_TIMxCMP1CR
HRTIM_TIMxCMP2R
HRTIM_TIMxCMP3R
HRTIM_TIMxCMP4R
HRTIM_DTxR
HRTIM_SETx1R
HRTIM_RSTx1R
HRTIM_SETx2R
HRTIM_RSTx2R
HRTIM_RSTxR
PREEN bit in
HRTIM_TIMxCR
Software
TIMx repetition event
TIMx reset event
Burst DMA event
Update event from other timers
(TIMy, master)
Update event following a burst
DMA event
Update enable inputs
hrtim_upd_en[3:1]
Update event following an update
enable input following an update
event on hrtim_upd_en[3:1] inputs
HRTIM
Common
HRTIM_ADC1R
HRTIM_ADC2R
HRTIM_ADC3R
HRTIM_ADC4R
TIMx or master timer Update, depending on
ADxUSRC[2:0] bits in HRTIM_CR1, if PREEN = 1 in the
selected timer
To Next Page
Loading...
Need help?
General
