ST STM32G491 User Manual

RM0440 Rev 4 97/2126
RM0440 Embedded Flash memory (FLASH) for category 3 devices
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After reset, the CPU clock frequency is 16 MHz and 1 wait state (WS) is configured in the
FLASH_ACR register.
When changing the CPU frequency, the following software sequences must be applied in
order to tune the number of wait states needed to access the Flash memory:
Increasing the CPU frequency:
1. Program the new number of wait states to the LATENCY bits in the Flash access
control register (FLASH_ACR).
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register.
3. Analyze the change of CPU frequency change caused either by:
– changing clock source defined by SW bits in RCC_CFGR register
– or by CPU clock prescaller defined by HPRE bits in RCC_CFGR
If some of above two steps decreases the CPU frequency, firstly perform this step and then
the rest. Otherwise modify The CPU clock source by writing the SW bits in the RCC_CFGR
register and then (if needed) modify the CPU clock prescaler by writing the HPRE bits in
RCC_CFGR.
4. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Decreasing the CPU frequency:
1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
3. Analyze the change of CPU frequency change caused either by:
– changing clock source defined by SW bits in RCC_CFGR register
– or by CPU clock prescaller defined by HPRE bits in RCC_CFGR
If some of above two steps increases the CPU frequency, firstly perform another step and
then this step. Otherwise modify The CPU clock source by writing the SW bits in the
Table 9. Number of wait states according to CPU clock (HCLK) frequency
Wait states (WS)
(LATENCY)
HCLK (MHz)
V
CORE
Range 1
boost mode
V
CORE
Range 1
normal mode
V
CORE
Range 2
0 WS (1 CPU cycles) ≤ 34 ≤ 30 ≤ 12
1 WS (2 CPU cycles) ≤ 68 ≤ 60 ≤ 24
2 WS (3 CPU cycles) ≤ 102 ≤ 90 ≤ 26
3 WS (4 CPU cycles) ≤ 136 ≤ 120 -
4 WS (5 CPU cycles) ≤ 170 ≤ 150 -

ST STM32G491 Specifications

General

Brand	ST
Model	STM32G491
Category	Microcontrollers
Language	English