General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0440
1248/2126 RM0440 Rev 4
Figure 377. Counter timing diagram, Update event with ARPE=1 (counter overflow)
29.4.5 Clock selection
The counter clock can be provided by the following clock sources:
• Internal clock (tim_ker_ck)
• External clock mode1: external input pin (tim_ti1 or tim_ti2)
• External clock mode2: external trigger input (tim_etr_in)
• Internal trigger inputs (tim_itr): using one timer as prescaler for another timer, for
example, Timer 1 can be configured to act as a prescaler for Timer 2. Refer to : Using
one timer as prescaler for another timer on page 1298 for more details.
Internal clock source (tim_ker_ck)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock tim_ker_ck.
Figure 378 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
MSv62315V1
FD
36
tim_psc_ck
tim_cnt_ck
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
36
34
33 32 31
30
2F
F8
F9
FA FB
FCF7
35
CEN
Auto-reload preload
register
Write a new value in TIMx_ARR
Auto-reload active
register
FD
36
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