RM0440 Rev 4 907/2126
RM0440 High-resolution timer (HRTIM)
1083
Each timer (TIMA..F) can also have the update done as follows:
• By software: writing 1 into TxSWU bit in HRTIM_CR2 forces an immediate update of
the registers. In this case, any pending hardware update request is canceled.
• Update done when the counter rolls over and the repetition counter is equal to 0. This
is enabled when TxREPU bit is set in HRTIM_TIMxCR.
• Update done when the counter is reset or rolls over in continuous mode. This is
enabled when TxRSTU bit is set in HRTIM_TIMxCR. This is used for a timer operating
in single-shot mode, for instance.
• Update done once a burst DMA is completed. This is enabled when
UPDGAT[3:0] = 0001 in HRTIM_TIMxCR.
• Update done on the update event following a burst DMA completion (the event can be
enabled with TxRSTU, TxREPU, MSTU or TxU). This is enabled when
UPDGAT[3:0] = 0010 in HRTIM_TIMxCR.
• Update done when receiving a request on hrtim_upd_en[3:1]. This is enabled when
UPDGAT[3:0] = 0011, 0100, 0101 in HRTIM_TIMxCR.
• Update done on the update event following a request on hrtim_upd_en[3:1] (the event
can be enabled with TxRSTU, TxREPU, MSTU or TxU). This is enabled when
UPDGAT[3:0] = 0110, 0111, 1000 in HRTIM_TIMxCR
• Update done synchronously with any other timer or master update (for instance TIMA
can be updated simultaneously with TIMB). This is used for converters requiring
several timers, and is enabled by setting bits MSTU and TxU in HRTIM_TIMxCR
register.
The update enable inputs hrtim_upd_en[3:1] allow to have an update event synchronized
with on-chip events coming from the general-purpose timers. These inputs are rising-edge
sensitive.
Table 209 lists the connections between update enable inputs and the on-chip sources.
This allows to synchronize low frequency update requests with high-frequency signals (for
instance an update on the counter roll-over of a 100 kHz PWM that has to be done at a
100 Hz rate).
Note: The update events are synchronized to the prescaler clock when CKPSC[2:0] > 5.
The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit
is set) or from a software update (TxSWU bit) can either be taken into account immediately
or re-synchronized with the timers reset/roll-over event. This is done with the RSYNCU bit in
the HRTIM_TIMxCR register, as show on Figure 232 below):
– RSYNCU = 0: The update coming from adjacent timers is taken into account
immediately
– RSYNCU = 1: The update coming from adjacent timers is taken into account on
the following reset/roll-over event.
The RSYNCU bit is significant only when UPDGAT[3:0] = 0000, it
is ignored otherwise.
An interrupt or a DMA request can be generated by the Timx update event.
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