Low-power universal asynchronous receiver transmitter (LPUART) RM0440
1726/2126 RM0440 Rev 4
38.6.8 LPUART interrupt and status register [alternate] (LPUART_ISR)
Address offset: 0x1C
Reset value: 0x0000 00C0
The same register can be used in FIFO mode enabled (previous section) and FIFO mode
disabled (this section).
FIFO mode disabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. REACK TEACK WUF RWU SBKF CMF BUSY
rrrrrrr
1514131211109876543210
Res. Res. Res. Res. Res. CTS CTSIF Res. TXE TC RXNE IDLE ORE NE FE PE
rr rrrrrrrr
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 REACK: Receive enable acknowledge flag
This bit is set/reset by hardware when the Receive Enable value is taken into account by the
LPUART.
It can be used to verify that the LPUART is ready for reception before entering low-power
mode.
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value.
Bit 21 TEACK: Transmit enable acknowledge flag
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the LPUART.
It can be used when an idle frame request is generated by writing TE=0, followed by TE=1
in the LPUART_CR1 register, in order to respect the TE=0 minimum period.
Bit 20 WUF: Wakeup from low-power mode flag
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register.
An interrupt is generated if WUFIE=1 in the LPUART_CR3 register.
Note: When UESM is cleared, WUF flag is also cleared.
If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value
Bit 19 RWU: Receiver wakeup from Mute mode
This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a
wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE)
is selected by the WAKE bit in the LPUART_CR1 register.
When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the
MMRQ bit in the LPUART_RQR register.
0: Receiver in active mode
1: Receiver in Mute mode
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value.
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