3.2 LSE oscillator clock
The advantage of using an external oscillator, it provides a low-power highly accurate clock source needed for
real-time clock (RTC), clock/calendar and other timing functions.
The LSE crystal oscillator has a configurable driving capability. This capability is chosen according to the external
resonator component to insure stable oscillation. It is based on the maximum critical crystal gm provide in the
datasheet (refer to Oscillator design guide for STM8S, STM8A and STM32 microcontrollers application note
(AN2867).
The driving capability is set through the LSEDRV [1:0] in RCC_BDCR register:
• 00: Low drive
• 10: Medium low drive
• 01: Medium high drive
• 11: High drive.
The LSERDY flag in the RCC backup domain control register (RCC_BDCR) indicates whether the LSE crystal is
stable or not. At start-up, the LSE crystal output clock signal is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the RCC clock interrupt register (RCC_CIER).
The LSE oscillator is switched on and off by programming the LSEON bit in RCC backup domain control register
(RCC_BDCR).
3.3 Clock security system (CSS)
The device provides two clock security systems (CSS), one for HSE oscillator and one for LSE oscillator. They
can be independently enabled by software.
When the clock security system on HSE is enabled, the clock detector is activated after the HSE oscillator start-
up delay, and disabled when this oscillator is stopped:
• If the HSE oscillator is used directly or indirectly as the system clock. Indirectly meaning that it is used as
PLL input clock, and the PLL clock is the system clock. When failure is detected, the system clock switches
to the HSI oscillator and the HSE oscillator is disabled.
• If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock failure event is sent
to the break inputs of the advanced-control timers TIM1, TIM8, TIM15, TIM16, and TIM17 and a non-mask-
able interrupt is generated to inform the software of the failure (clock security system interrupt
rcc_hsecss_it), allowing the MCU to perform the rescue operations needed. The rcc_hsecss_it is linked to
the Arm
®
Cortex
®
-M7 NMI (non-maskable interrupt) exception vector.
• If the HSE oscillator clock was used as PLL clock source, the PLL is also disabled when the HSE fails.
The clock security system on LSE must be enabled only when the LSE is enabled and ready, and after the RTC
clock has been selected through the RTCSRC[1:0] bits of RCC_BDCR register.
When an LSE failure is detected, the CSS on the LSE wakes the device up from all low-power modes except
V
BAT
. If the failure occurred in V
BAT
mode, the software can check the failure detection bit when the device is
powered on again. In all cases the software can select the best behavior to adopt (including disabling the CSS on
LSE which is not automatic).
3.4 Clock recovery system (CRS)
The clock recovery system (CRS) is dedicated to the internal HSI48 RC oscillator.
The CRS is an advanced digital controller acting on the internal fine-granularity trim resulting in a very precise
48 MHz clock.
The CRS is ideally suited to provide a precise clock for the USB peripheral.
The CRS requires a synchronization signal.
Three possible sources are selectable with programmable pre-scaler and polarity:
• SYNC external signal provided through pin;
• LSE oscillator output;
• USB SOF packet reception.
For more details refer to the reference manual STM32H723/733, STM32H725/735 and STM32H730 advanced
Arm
®
-based 32-bit MCUs (RM0468).
AN5419
LSE oscillator clock
AN5419 - Rev 2
page 23/50
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