ST STM32H74xI/G User Manual

Debug management AN4938
30/46 AN4938 Rev 4
6.3.2 Flexible SWJ-DP pin assignment
After RESET (SYSRESETn or PORESETn), all the five pins used for the SWJ-DP are
assigned as dedicated pins immediately usable by the debugger host (note that the trace
outputs are not assigned except if explicitly programmed by the debugger host).
However, the STM32H74xI/G and STM32H75xI/G devic
es offer the possibility of disabling
some or all of the SWJ-DP ports and so, of releasing the associated pins for general-
purpose IO (GPIO) usage.
Table 7 s
hows the different possibilities to release some pins.
For more details on how to disable SWJ-DP port pins, please refer to the reference manual
I/O pin alternate function multiplexer and mapping section.
Table 6. SWJ debug port pins
SWJ-DP pin name
JTAG debug port SW debug port
Pin
assignment
Type Description Type Debug assignment
JTMS/SWDIO I
JTAG test mode
Selection
IO
Serial wire data
input/output
PA13
JTCK/SWCLK I JTAG test clock I Serial wire clock PA14
JTDI I JTAG test data input - - PA15
JTDO/TRACESWO O
JTAG test data
output
-
TRACESWO if
asynchronous trace is
enabled
PB3
NJTRST I JTAG test nReset - - PB4
Table 7. Flexible SWJ-DP assignment
Available debug ports
SWJ IO pin assigned
PA13/
JTMS/
SWDIO
PA14/JTCK
/SWCLK
PA15/JTDI PB3/JTDO PB4/NJTRST
Full SWJ (JTAG-DP + SW-DP) - reset state X X X X X
Full SWJ (JTAG-DP + SW-DP) but without
NJTRST
XXXX
-
JTAG-DP disabled and SW-DP enabled X X -
JTAG-DP disabled and SW-DP disabled Released

ST STM32H74xI/G Specifications

General

Brand	ST
Model	STM32H74xI/G
Category	Microcontrollers
Language	English

Summary

Introduction

Reference documents

1 General information

2 Power supplies

2.1 Introduction

Introduces the power supply aspects and considerations for STM32H7xx devices.

2.2 Power supply scheme

Outlines the overall power supply architecture, external connections, and decoupling.

2.3 Reset and power supply supervisor

Explains reset sources, power-on/down resets, and voltage supervisors.

3 Alternate function mapping to pins

4 Clocks

4.1 HSE oscillator clock

Covers High-Speed External oscillator clock options: bypass and crystal.

4.2 LSE oscillator clock

Describes Low-Speed External oscillator clock options: bypass and crystal.

4.3 Clock security system (CSS)

Explains the clock security system for detecting HSE and LSE clock failures.

5 Boot configuration

5.1 Boot mode selection

Details how to select boot modes using BOOT pin and option bytes.

5.2 Boot pin connection

Explains the external connection required for boot mode selection.

5.3 System bootloader mode

Describes the system bootloader and its communication peripherals.

6 Debug management

6.1 Introduction

Introduces the host/target interface and its components for debugging.

6.2 SWJ debug port (serial wire and JTAG)

Details the Serial Wire/JTAG Debug Port (SWJ-DP) and its interfaces.

6.3 Pinout and debug port pins

Discusses pin configurations related to debugging and debug ports.

7 Recommendations

7.1 Printed circuit board

Guidelines for PCB layout, layers, and grounding.

7.2 Component position

Recommendations for component placement to reduce EMI and cross-coupling.

7.3 Ground and power supply (VSS,VDD)

Best practices for ground and power supply routing and loop minimization.

7.4 Decoupling

Explains decoupling capacitor placement, types, and impedance considerations.

7.5 Other signals

Tips for managing other signals like noisy and sensitive signals for EMC.

7.6 Unused I/Os and features

Strategies for handling unused MCU resources to improve EMC performance.

8 Reference design

8.1 Reference design description

Describes the core components, clock sources, reset, boot mode, SWJ, and power supply of the reference design.

8.2 Component references

Lists mandatory and optional components used in the reference design.

9 Recommended PCB routing guidelines for STM32H74xl/G and STM32H75xl/G devices

9.1 PCB stack-up

Details different PCB layer stack-up configurations for impedance matching and EMC.

9.2 Crystal oscillator

Offers guidance on layout and routing of crystal oscillator circuits.

9.3 Power supply decoupling

Explains power supply decoupling best practices to prevent noise.

9.4 High speed signal layout

Guides on layout for high-speed signal integrity, including SDMMC, FMC, QUADSPI, ETM.

10 Conclusion

11 Revision history