AN4938 Rev 4 41/46
AN4938 Recommended PCB routing guidelines for STM32H74xI/G and STM32H75xI/G devices
45
Interface signal layout guidelines
• Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR
and GND
• Trace the impedance: 50 Ω ± 10%
• The maximum trace length should be below 120
mm. If the signal trace exceeds this
trace-length/speed criterion, then a termination should be used
• Reduce the crosstalk, place data tracks on the different layers from the address and
control lanes, if
possible. However, when the data and address/control tracks coexist
on the same layer they must be isolated from each other by at least 5 mm.
• Match the trace lengths for the data group within ± 10 mm of each other to diminish the
ske
w. Serpentine traces (back and forth traces in an “S” pattern to increase trace
length) can be used to match the lengths.
• Placing the clock (SDCLK) signal on an inter
nal layer, minimizes the noise (EMI).
Route the clock signal at least 3x of the trace away from others signals. Use as less
vias as possible to avoid impedance change and reflection. Avoid using serpentine
routing.
• Match the clock traces to the data/a
ddress group traces within ±10mm.
• Match the clock traces to each signal trace in th
e address and command groups to
within ±10mm (with maximum of <= 20 mm).
• Trace the capacitances:
– At 3.3 V keep the trace within 20 pF with overall capacitive loading (including Data,
Ad
dress, SDCLK and Control) no more than 30 pF.
– At 1.8 V keep the trace within 15 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 20 pF.
9.4.3 Quadrature serial parallel interface (QUADSPI)
Interface connectivity
The QUADSPI is a specialized communication interface targeting single, dual or QUADSPI
FLASH memories. The QUADSPI interface is a serial data bus interface, that consists of a
clock (SCLK), a chip select signal (nCS) and 4 data lines (IO[0:3]).
b.It depends of the used memory: SDRAM with x8 bus widths have only one data group,
while x16 and x32 bus-width SDRAM have two and four lanes, respectively.
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