ST STM32H74xI/G User Manual

AN4938 Rev 4 41/46
AN4938 Recommended PCB routing guidelines for STM32H74xI/G and STM32H75xI/G devices
45
Interface signal layout guidelines
• Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR
and GND
• Trace the impedance: 50 Ω ± 10%
• The maximum trace length should be below 120
mm. If the signal trace exceeds this
trace-length/speed criterion, then a termination should be used
• Reduce the crosstalk, place data tracks on the different layers from the address and
control lanes, if
possible. However, when the data and address/control tracks coexist
on the same layer they must be isolated from each other by at least 5 mm.
• Match the trace lengths for the data group within ± 10 mm of each other to diminish the
ske
w. Serpentine traces (back and forth traces in an “S” pattern to increase trace
length) can be used to match the lengths.
• Placing the clock (SDCLK) signal on an inter
nal layer, minimizes the noise (EMI).
Route the clock signal at least 3x of the trace away from others signals. Use as less
vias as possible to avoid impedance change and reflection. Avoid using serpentine
routing.
• Match the clock traces to the data/a
ddress group traces within ±10mm.
• Match the clock traces to each signal trace in th
e address and command groups to
within ±10mm (with maximum of <= 20 mm).
• Trace the capacitances:
– At 3.3 V keep the trace within 20 pF with overall capacitive loading (including Data,
Ad
dress, SDCLK and Control) no more than 30 pF.
– At 1.8 V keep the trace within 15 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 20 pF.
9.4.3 Quadrature serial parallel interface (QUADSPI)
Interface connectivity
The QUADSPI is a specialized communication interface targeting single, dual or QUADSPI
FLASH memories. The QUADSPI interface is a serial data bus interface, that consists of a
clock (SCLK), a chip select signal (nCS) and 4 data lines (IO[0:3]).
b.It depends of the used memory: SDRAM with x8 bus widths have only one data group,
while x16 and x32 bus-width SDRAM have two and four lanes, respectively.

ST STM32H74xI/G Specifications

General

Brand	ST
Model	STM32H74xI/G
Category	Microcontrollers
Language	English

Summary

Introduction

Reference documents

1 General information

2 Power supplies

2.1 Introduction

Introduces the power supply aspects and considerations for STM32H7xx devices.

2.2 Power supply scheme

Outlines the overall power supply architecture, external connections, and decoupling.

2.3 Reset and power supply supervisor

Explains reset sources, power-on/down resets, and voltage supervisors.

3 Alternate function mapping to pins

4 Clocks

4.1 HSE oscillator clock

Covers High-Speed External oscillator clock options: bypass and crystal.

4.2 LSE oscillator clock

Describes Low-Speed External oscillator clock options: bypass and crystal.

4.3 Clock security system (CSS)

Explains the clock security system for detecting HSE and LSE clock failures.

5 Boot configuration

5.1 Boot mode selection

Details how to select boot modes using BOOT pin and option bytes.

5.2 Boot pin connection

Explains the external connection required for boot mode selection.

5.3 System bootloader mode

Describes the system bootloader and its communication peripherals.

6 Debug management

6.1 Introduction

Introduces the host/target interface and its components for debugging.

6.2 SWJ debug port (serial wire and JTAG)

Details the Serial Wire/JTAG Debug Port (SWJ-DP) and its interfaces.

6.3 Pinout and debug port pins

Discusses pin configurations related to debugging and debug ports.

7 Recommendations

7.1 Printed circuit board

Guidelines for PCB layout, layers, and grounding.

7.2 Component position

Recommendations for component placement to reduce EMI and cross-coupling.

7.3 Ground and power supply (VSS,VDD)

Best practices for ground and power supply routing and loop minimization.

7.4 Decoupling

Explains decoupling capacitor placement, types, and impedance considerations.

7.5 Other signals

Tips for managing other signals like noisy and sensitive signals for EMC.

7.6 Unused I/Os and features

Strategies for handling unused MCU resources to improve EMC performance.

8 Reference design

8.1 Reference design description

Describes the core components, clock sources, reset, boot mode, SWJ, and power supply of the reference design.

8.2 Component references

Lists mandatory and optional components used in the reference design.

9 Recommended PCB routing guidelines for STM32H74xl/G and STM32H75xl/G devices

9.1 PCB stack-up

Details different PCB layer stack-up configurations for impedance matching and EMC.

9.2 Crystal oscillator

Offers guidance on layout and routing of crystal oscillator circuits.

9.3 Power supply decoupling

Explains power supply decoupling best practices to prevent noise.

9.4 High speed signal layout

Guides on layout for high-speed signal integrity, including SDMMC, FMC, QUADSPI, ETM.

10 Conclusion

11 Revision history