ADC and DAC reference voltage
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to VREF+ pin, a separate
reference voltage lower than V
DDA
.
V
REF+
is the highest voltage, represented by the full-scale value, for an analog input (ADC) or output (DAC)
signal. V
REF+
can be provided either by an external reference or by the VREFBUF, that can output a configurable
voltage: 1.5, 1.8, 2.048 or 2.5 V. The VREFBUF can also provide the voltage to external components through the
VREF+ pin.
For further information, refer to the device datasheet and section 'Voltage reference buffer (VREFBUF)' of the
reference manual.
2.1.2 Independent I/O supply rail
Some I/Os from port G (PG[15:2]) are supplied from a separate supply rail. The power supply for this rail can
range from 1.08 V to 3.6 V, and is provided externally through the VDDIO2 pin. The V
DDIO2
voltage level is
completely independent from V
DD
or V
DDA
.
The VDDIO2 pin is available only for some packages (refer to the pinout details in the datasheet for the I/O list).
After reset, the I/Os supplied by V
DDIO2
are logically and electrically isolated and are therefore not available. The
isolation must be removed before using any I/O from PG[15:2], by setting the IO2SV bit in PWR_SVMR register,
once the V
DDIO2
supply is present.
The V
DDIO2
supply is monitored by the V
DDIO2
voltage monitoring (IO2VM) and compared with the internal
reference voltage (3/4 V
REFINT
, around 0.9 V).
For more details, refer to the device datasheet and section 'Peripheral voltage monitoring (PVM)' of the reference
manual .
2.1.3 Independent USB transceiver supply
The USB transceivers are supplied from a separate V
DDUSB
power supply. V
DDUSB
range is from 3.0 V to 3.6 V
and is completely independent from V
DD
or V
DDA
.
After reset, the USB features supplied by V
DDUSB
are logically and electrically isolated, and are therefore not
available. The isolation must be removed before using the USB OTG peripheral, by setting the USV bit in the
PWR_SVMR register, once the V
DDUSB
supply is present.
The V
DDUSB
supply is monitored by the USB voltage monitoring (UVM) and compared with the internal reference
voltage (V
REFINT
, around 1.2 V). For more details, refer to the device datasheet and section 'Peripheral voltage
monitoring (PVM)' of the product reference manual .
2.1.4 Battery Backup domain
To retain the content of the backup registers and supply the RTC when V
DD
is turned off, the VBAT pin can be
connected to an optional backup voltage, supplied by a battery or by another source.
The VBAT pin powers RTC, TAMP, LSE oscillator and PC13 to PC15 I/Os, allowing the RTC to operate even
when the main power supply is turned off.
The backup SRAM is optionally powered through the VBAT pin, when the BREN bit is set in the PWR_BDCR1
register.
The switch to the V
BAT
supply is controlled by the power-down reset embedded in the Reset block.
Caution: • During t
RSTTEMPO
(at V
DD
startup) or after a PDR (power-down reset) detection, the power switch between
V
BAT
and V
DD
remains connected to VBAT pin.
• During the startup phase, if V
DD
is established in less than t
RSTTEMPO
(refer to the datasheet for t
RSTTEMPO
value), and V
DD
> V
BAT
+ 0.6 V, a current may be injected into VBAT pin through an internal diode
connected between the VDD pin and the power switch (VBAT). If the power supply/battery connected to
the VBAT pin cannot support this current injection, it is strongly recommended to connect an external
low-drop diode between this power supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect the VBAT pin externally to V
DD
with
a 100 nF external ceramic decoupling capacitor.
AN5373
Power supplies
AN5373 - Rev 1
page 6/37
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