Single wire interface module (SWIM) UM0470
18/39 DocID14024 Rev 4
3.10 STM8 MCUs SWIM registers
3.10.1 SWIM control status register (SWIM_CSR)
Address: 7F80h
Reset value: 00h
This register is reset only by a power on reset or by a SWIM SRST command if the RST
bit
=1 in the SWIM_CSR register.
76543210
SAFE_MASK NO_ACCESS SWIM_DM HS OSCOFF RST HSIT PRI
rw r rwrwrwrw r rw
Bit 7
SAFE_MASK: Mask internal RESET sources
This bit can be read or written through the SWIM only. It cannot be accessed through
the STM8 bus. It includes the watchdog reset.
0: Internal reset sources are not masked
1: Internal reset sources are masked.
Bit 6
NO_ACCESS: Bus not accessible
This bit can be read through the SWIM only, to determine if the bus is accessible or
not. It is set automatically if the device is in HALT, WFI or readout protection mode.
0: Bus is accessible
1: Bus is not accessible
Caution: Depending on the SWIM revision, in some devices, the NO_ACCESS bit
indicates only that the device is in HALT mode.
Bit 5
SWIM_DM: SWIM for debug module
This bit can be read or written to 1 through the SWIM only. It cannot be accessed
through the STM8 bus.
0: The SWIM can access only the SWIM_CSR register. The SWIM reset command
has no effect
1: The whole memory range can be accessed with the ROTF and WOTF commands.
The SRST command generates a reset.
Bit 4
HS: High speed
This bit can be read or written through the SWIM only. It cannot be accessed through
the STM8 bus.
0: Low speed bit format
1: High speed bit format
The speed change occurs when the communication is IDLE. It is reset by the SWIM
communication reset condition as described in Section 3.6.
Bit 3
OSCOFF: Oscillators off control bit
This bit can be read or written through the SWIM only. It cannot be accessed through
the STM8 bus.
0: HSI oscillator remains ON in Halt mode
1: HSI oscillator is not requested ON in Halt mode
To Next Page
Loading...
Need help?
General
