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Debug module (DM) UM0470

30/39 DocID14024 Rev 4

4.12.7 DM control register 1 (DM_CR1)

Address: 7F96h

Reset value: 0000 0000 (00h)

WDGOFF Reserved BC[2:0] BIR BIW Reserved

76543210

rw - rw rw rw rw rw -

Bit 7

WDGOFF Watchdog control enable.

This bit must be set or cleared by software before the watchdogs (WWDG and/or

IWDG) are activated. This bit has no effect if the hardware watchdog option is

selected.

0: Watchdog counters are not stopped while the CPU is stalled by DM

1: Watchdog counters are stopped while the CPU is stalled by DM

Bit 6 Reserved.

Bits 5:3

BC[2:0] Breakpoint control

These bits are set and cleared by software, they are used to configure the breakpoints

as shown in Tab le 4.

Bit 2

BIR Break on read control

This bit enables a breakpoint on a data read operation. It is set and cleared by

software.

0: No break on data read

1: Break on data read

Bit 1

BIW Break on write control

This bit enables a breakpoint on a data write operation. It is set and cleared by

software.

0: No break on data write

1: Break on data write

Bit 0 Reserved.

ST STM8 User Manual

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