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ST STM8 User Manual
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Debug module (DM)
UM0470
26/39
DocID14024 Rev 4
Figure 16. STM8 DM step timing
Note:
When the S
tep mode and the
instruction break
on the next instruction mode are
both
enabled, both the STF and the BKxF flags a
re se
t. When the user clears the ST
ALL bit, the
step function continues it
s normal operation.
25
27
Table of Contents
Table of Contents
2
Debug System Overview
6
Figure 1. Debug System Block Diagram
6
Communication Layer
7
Figure 2. SWIM Pin External Connections
7
Single Wire Interface Module (SWIM)
8
Operating Modes
8
Figure 3. SWIM Activation Sequence
8
SWIM Entry Sequence
9
Figure 4. SWIM Activation Timing Diagram
9
Figure 5. SWIM Entry Sequence
10
Bit Format
11
High Speed Bit Format
11
Figure 6. High Speed Bit Format
11
Low Speed Bit Format
12
Figure 7. Low Speed Bit Format
12
SWIM Communication Protocol
13
Figure 8. Command Format (Host -> Target)
13
Figure 9. Data Format (Target -> Host)
13
SWIM Commands
14
SRST: System Reset
14
ROTF: Read On-The-Fly
14
Table 1. SWIM Command Summary
14
WOTF: Write On-The-Fly
15
SWIM Communication Reset
15
CPU Register Access
16
SWIM Communication in Halt Mode
16
Table 2. CPU Register Memory Mapping in STM8 Mcus
16
Physical Layer
17
Table 3. SWIM Pin Characteristics
17
Figure 10. Timings on the SWIM Pin
17
STM8 Mcus SWIM Registers
18
SWIM Control Status Register (SWIM_CSR)
18
SWIM Clock Control Register (CLK_SWIMCCR)
19
Debug Module (DM)
20
Introduction
20
Main Features
20
Figure 11. Debug Module Block Diagram
21
Debug
22
Reset
22
Breakpoints
22
Abort
22
Watchdog Control
22
Interaction with SWIM
22
Breakpoint Decoding Table
23
Table 4. Decoding Table for Breakpoint Interrupt Generation
23
Software Breakpoint Mode
24
Timing Description
24
Abort
24
Figure 12. STM8 MCU Instruction Model
24
Figure 13. STM8 Debug Module Stall Timing
24
Data Breakpoint
25
Instruction Breakpoint
25
Step Mode
25
Figure 14. STM8 DM Data Breaktiming
25
Figure 15. STM8 DM Instruction Break Timing
25
Figure 16. STM8 DM Step Timing
26
Application Notes
27
Illegal Memory Access
27
Forbidden Stack Access
27
DM Break
27
DM Registers
28
DM Breakpoint Register 1 Extended Byte (DM_BKR1E)
28
DM Breakpoint Register 1 High Byte (DM_BKR1H)
28
DM Breakpoint Register 1 Low Byte (DM_BKR1L)
28
DM Breakpoint Register 2 Extended Byte (DM_BKR2E)
29
DM Breakpoint Register 2 High Byte (DM_BKR2H)
29
DM Breakpoint Register 2 Low Byte (DM_BKR2L)
29
DM Control Register 1 (DM_CR1)
30
DM Control Register 2 (DM_CR2)
31
DM Control/Status Register 1 (DM_CSR1)
32
DM Control/Status Register 2 (DM_CSR2)
33
DM Enable Function Register (DM_ENFCTR)
34
Summary of SWIM, DM and Core Register Maps
35
Table 5. STM8 MCU Registers
35
Appendix A Description of the DM_ENFCTR Register
37
For each STM8 Product
37
Table 6. Peripherals Which Are Frozen by the Bits of the DM_ENFCTR Register
37
Revision History
38
Table 7. Document Revision History
38
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ST STM8 Specifications
General
Brand
ST
Model
STM8
Category
Control Unit
Language
English
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