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Debug module (DM) UM0470

26/39 DocID14024 Rev 4

Figure 16. STM8 DM step timing

Note: When the Step mode and the instruction break on the next instruction mode are both

enabled, both the STF and the BKxF flags are set. When the user clears the STALL bit, the

step function continues its normal operation.

Main Page

Table of Contents2
Debug System Overview6
Figure 1. Debug System Block Diagram6
Communication Layer7
Figure 2. SWIM Pin External Connections7
Single Wire Interface Module (SWIM)8
Operating Modes8
Figure 3. SWIM Activation Sequence8
SWIM Entry Sequence9
Figure 4. SWIM Activation Timing Diagram9
Figure 5. SWIM Entry Sequence10
Bit Format11
High Speed Bit Format11
Figure 6. High Speed Bit Format11
Low Speed Bit Format12
Figure 7. Low Speed Bit Format12
SWIM Communication Protocol13
Figure 8. Command Format (Host -> Target)13
Figure 9. Data Format (Target -> Host)13
SWIM Commands14
SRST: System Reset14
ROTF: Read On-The-Fly14
Table 1. SWIM Command Summary14
WOTF: Write On-The-Fly15
SWIM Communication Reset15
CPU Register Access16
SWIM Communication in Halt Mode16
Table 2. CPU Register Memory Mapping in STM8 Mcus16
Physical Layer17
Table 3. SWIM Pin Characteristics17
Figure 10. Timings on the SWIM Pin17
STM8 Mcus SWIM Registers18
SWIM Control Status Register (SWIM_CSR)18
SWIM Clock Control Register (CLK_SWIMCCR)19
Debug Module (DM)20
Introduction20
Main Features20
Figure 11. Debug Module Block Diagram21
Debug22
Reset22
Breakpoints22
Abort22
Watchdog Control22
Interaction with SWIM22
Breakpoint Decoding Table23
Table 4. Decoding Table for Breakpoint Interrupt Generation23
Software Breakpoint Mode24
Timing Description24
Abort24
Figure 12. STM8 MCU Instruction Model24
Figure 13. STM8 Debug Module Stall Timing24
Data Breakpoint25
Instruction Breakpoint25
Step Mode25
Figure 14. STM8 DM Data Breaktiming25
Figure 15. STM8 DM Instruction Break Timing25
Figure 16. STM8 DM Step Timing26
Application Notes27
Illegal Memory Access27
Forbidden Stack Access27
DM Break27
DM Registers28
DM Breakpoint Register 1 Extended Byte (DM_BKR1E)28
DM Breakpoint Register 1 High Byte (DM_BKR1H)28
DM Breakpoint Register 1 Low Byte (DM_BKR1L)28
DM Breakpoint Register 2 Extended Byte (DM_BKR2E)29
DM Breakpoint Register 2 High Byte (DM_BKR2H)29
DM Breakpoint Register 2 Low Byte (DM_BKR2L)29
DM Control Register 1 (DM_CR1)30
DM Control Register 2 (DM_CR2)31
DM Control/Status Register 1 (DM_CSR1)32
DM Control/Status Register 2 (DM_CSR2)33
DM Enable Function Register (DM_ENFCTR)34
Summary of SWIM, DM and Core Register Maps35
Table 5. STM8 MCU Registers35
Appendix A Description of the DM_ENFCTR Register37
For each STM8 Product37
Table 6. Peripherals Which Are Frozen by the Bits of the DM_ENFCTR Register37
Revision History38
Table 7. Document Revision History38

Table of Contents

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