Debug module (DM) UM0470
34/39 DocID14024 Rev 4
4.12.11 DM enable function register (DM_ENFCTR)
Address: 7F9Ah
Reset Value: 1111 1111 (FFh)
See Appendix A for a full description of the DM_ENFCTR register.
7 0
ENFCT7 ENFCT6 ENFCT5 ENFCT4 ENFCT3 ENFCT2 ENFCT1 ENFCT0
rw rw rw rw rw rw rw rw
Bits 7:0
ENFCTx Enable function
This bit is set and cleared by software. it allows to freeze a particular function of a
peripheral when the core is stalled. The ENFCTx bit definitions are product
dependent.
0: Function is frozen when the CPU is stalled by a DM
1: Function is active
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