DocID14024 Rev 4 33/39
UM0470 Debug module (DM)
38
4.12.10 DM control/status register 2 (DM_CSR2)
Address: 7F99h
Reset value: 0000 0000 (00h)
Reserved SWBRK SWBKF STALL Reserved FLUSH
Reserved. it must be kept at 0
FLUSH Fl
ush decode
76543210
rw r r rw
Bits 7:6 Reserved. It must be kept at 0
Bit 5
SWBKE Software breakpoint control bit (read/write)
This bit is used to enable/disable the software breakpoint capability with NOP
instruction
0: DM does not generate any event when NOP(SW BRK) instruction is fetched by the
CPU
1: DM generates an event (CPU stalled in SWIM mode) when a software break
instruction is fetched by the CPU.
Bit 4
SWBKF Software breakpoint status bit (read only)
This flag is set when the CPU executes the software break instruction.
0: No software break instruction detected.
1: Software break instruction detected. This bit is cleared when the STALL bit is
cleared.
Bit 3
STALL CPU stall control bit (read/write only in SWIM mode)
This bit is used to stall the CPU. This bit is kept cleared if the device is not in SWIM
mode.
This bit is set by WOTF command to generate an ABORT equivalent command.
It is also set by an DM trap interrupt event.
This bit is cleared by WOTF command to re-start the CPU.
0: CPU runs normally
1: CPU is stalled
Bit: 2:1
Bit: 10
This bit is set by software to flush the instruction decode phase after a PC
mo
dification. It is cleared by hardware when the flush is completed.
0: Default status
1: Flush decode
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