DocID14024 Rev 4 19/39
UM0470 Single wire interface module (SWIM)
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3.10.2 SWIM clock control register (CLK_SWIMCCR)
Address Offset: 50CDh (product dependent)
Reset value: xxxx 0000 (x0h)
Bit 2
RST: SWIM reset control bit
This bit can be read or written through the SWIM only. It cannot be accessed through
the STM8 bus.
0: SWIM is not reset when a SRST command occurs.
1: SWIM is reset when a SRST command occurs. The SWIM will re-enter OFF mode.
Bit 1
HSIT: High speed internal clock is trimmed
This bit is read only through SWIM only. It cannot be accessed through STM8 bus. It is
set when the HSIT bit is set in the core configuration register and reset by an external
reset.
0: High speed internal clock is not trimmed, the SWIM must remain in low speed
mode.
1: High speed internal clock is trimmed, the SWIM high speed mode is allowed.
Bit 0
PRI: SWIM access priority
This bit can be read or written through the SWIM only. Usually the SWIM accesses to
system resources are non-intrusive, the SWIM having the lowest priority. This can be
overridden by setting this bit.
0: Non-intrusive access by the SWIM to system resources (low priority)
1: Intrusive access by the SWIM to system resources (SWIM has the priority, the CPU
is stalled).
Note: The SWD bit is located in the STM8 core configuration register. Refer to the
corresponding datasheet for information on this register
76543210
Reserved SWIMCLK
- rw
Bits 7:1 Reserved, must be kept cleared.
Bit 0
SWIMCLK SWIM clock divider
This bit is set and cleared by software.
0: SWIM clock is divided by 2 (recommended)
1: SWIM clock is not divided by 2 (not recommended as communication is less
reliable)
Note: this register is not present in some STM8 devices.
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