ST STM8 User Manual

Debug module (DM) UM0470
32/39 DocID14024 Rev 4
4.12.9 DM control/status register 1 (DM_CSR1)
Address: 7F98h
Reset value: 0001 0000 (10h)
76543210
Reserved STE STF RST BRW BK2F BK1F Reserved
rwrwrrrr
Bit 7 Reserved.
Bit 6
STE Step mode enable (read / write)
This bit is set and cleared by software. It enables the Step mode.
0: Step mode disabled
1: Step mode enabled
Bit 5
STF Step flag (read only)
This bit indicates that the stall was generated by the Step mode. It is set and cleared
by hardware. Writing to this bit does not change the bit value.
0: Step mode stall did not occur
1: Step mode stall occurred
Bit 4
RST Reset flag (read only)
This bit is set by hardware when the CPU was stalled by the debug module (DM), just
after reset. It is cleared by hardware when the STALL bit is cleared. Writing to this bit
does not change the bit value.
0: No reset occurred
1: A reset occurred
Bit 3
BRW Break on read/write flag (read only).
This bit gives the value of the read/write signal when a break occurs. Its value is not
significant for the instruction fetch breaks. It is set by hardware depending on the
breakpoint conditions (see Table 4: Decoding table for breakpoint interrupt generation
on page 23) and is cleared by hardware depending on the next breakpoint conditions.
Writing to this bit does not change the bit value.
0: Breakpoint on write
1: Breakpoint on read
Bit 2
BK2F Breakpoint 2 flag (read only).
This bit indicates that the DM stall was generated by breakpoint 2. It is set by
hardware depending on the control conditions (see Table 4: Decoding table for
breakpoint interrupt generation on page 23) and it is cleared by hardware when the
STALL bit is cleared. Writing to this bit does not change the bit value.
0: Breakpoint 2 did not occur
1: Breakpoint 2 occurred
Bit 1
BK1F Breakpoint 1 flag (read only).
This bit indicates that the DM interrupt was generated by breakpoint 1. It is set by
hardware depending on the control conditions (see Table 4: Decoding table for
breakpoint interrupt generation on page 23) and it is cleared by hardware when the
STALL bit is cleared. Writing to this bit does not change the bit value.
0: Breakpoint 1 did not occur
1: Breakpoint 1 occurred
Bit 0 Reserved

ST STM8 Specifications

General

Brand	ST
Model	STM8
Category	Control Unit
Language	English