ST STM8

DocID14024 Rev 4 25/39
UM0470 Debug module (DM)
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4.8 Data breakpoint
A stall is generated when the SWIM is active, and after the end of the current instruction
execution.
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Figure 14. STM8 DM data breaktiming
4.9 Instruction breakpoint
In the STM8 devices, with an instruction break, DM stalls the CPU before the selected
instruction execution (while the instruction is in the decode stage). See Figure 15.
Note: When the specified address does not correspond
to a valid instruction address, no stall is
generated.
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Figure 15. STM8 DM instruction break timing
4.10 Step mode
The STM8 CPU stall is activated before the instruction execution, in the first decode cycle of
the instruction. See Figure 16.