Supermicro SuperServer 4029GP-TRT - Page 86

SuperServer 4029GP-TRT/TRT2/TRT3 User's Manual
86
IIO Conguration
EV DFX (Device Function On-Hide) Features
When this feature is set to Enable, the EV_DFX Lock Bits that are located in a processor
will always remain clear during electric tuning. The options are Disable and Enable.
CPU1 Conguration/CPU2 Conguration
IOU0 (IIO PCIe Br1)

The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.
IOU1 (IIO PCIe Br2)

The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.
IOU2 (IIO PCIe Br3)

The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.
MCP0 (IIO PCIe Br4)

The options are x16 and Auto.
MCP1 (IIO PCIe Br5)

The options are x16 and Auto.
CPU1 PCI-E Br0D00F0 - Port 0/DMI (Available for CPU 1 Conguration
only)
Link Speed

are Auto, Gen 1 (Generation 1) (2.5 GT/s), Gen 2 (Generation 2) (5 GT/s), and Gen 3
(Generation 3) (8 GT/s)
The following information will be displayed as well:
• PCI-E Port Link Status
• PCI-E Port Link Max
• PCI-E Port Link Speed
PCI-E Port Clocking (Available for CPU 1 Conguration only)

and downstream components. The options are Distinct and Common.