Supermicro X10SRM-F - Page 85

Chapter 4: BIOS
85
CPU1 SLOT5 PCI-E 3.0 X8 Link Speed
This feature allows the user to select PCI-E support for the device installed on SLOT5. The
options are Auto, Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).
Onboard LAN Link Speed
This feature allows the user to select the link speeds for the onboard LAN ports. The options
are Auto, Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).
IIO1 IOU0 Non-Posted Prefetch
Use this feature to disable non-posted prefetch for IOU0 ports 2A and 2B. The IIO will make
prefetches to read streams of data ahead of the I/O device. Set this feature to Disabled to
keep the bit to the default value 1. Set this feature to Enabled to keep the bit value at 0,
a negative logic. The options are Enable and Disable.
IIO1 IOU1 Non-Posted Prefetch
Use this feature to disable non-posted prefetch for IOU0 ports 3A and 3B. The IIO will make
prefetches to read streams of data ahead of the I/O device. Set this feature to Disabled to
keep the bit to the default value 1. Set this feature to Enabled to keep the bit value at 0,
a negative logic. The options are Enable and Disable.
IIO1 IOU2 Non-Posted Prefetch
Use this feature to disable non-posted prefetch for IOU0 port 1. The IIO will make prefetches
to read streams of data ahead of the I/O device. Set this feature to Disabled to keep the
bit to the default value 1. Set this feature to Enabled to keep the bit value at 0, a negative
logic. The options are Enable and Disable.
IOAT (Intel
®
IO Acceleration) Conguration
Enable IOAT
Select Enable to enable Intel I/OAT (I/O Acceleration Technology) support, which signicantly
reduces CPU overhead by leveraging CPU architectural improvements and freeing the
system resource for other tasks. The options are Disable and Enable.
No Snoop
Select Enable to support no-snoop mode for each CB device. The options are Disable
and Enable.
Relaxed Ordering
Select Enable to enable Relaxed Ordering support which will allow certain transactions to
violate the strict-ordering rules of PCI bus for a transaction to be completed prior to other
transactions that have already been enqueued. The options are Disable and Enable.