Tait TB9100 - Page 119

TB9100 Reciter Service Manual Appendices 119
© Tait Electronics Limited January 2006
REJECT1
SPISEL
PB31
C17 I/O SCC1 CAM interface reject pin
SPI client select input
General-purpose I/O port B, bit 31
RSTCONF P3 I/P Reset Configuration
RSTRT1
PB14
RXADDR2
U18 I/O SCC1 serial CAM interface outputs that marks the start of a frame
General-purpose I/O port B, bit 14
UTOPIA multi-PHY receive address line 2
L1ST1
RTS1
DREQ0
PC15
Rxclav
D16 I/O Output strobes from the serial interface
Request to send modem line for SCC1
IDMA channel 1 request input
General-purpose I/O port C, bit 15
Receive cell available input signal
RxD1
PA15
D17 I/O SCC1 Receive Data input
General-purpose I/O port A, bit 15
SDACK1
L1TSYNCA
PC5
T18 I/O SDMA acknowledge 1output
Transmit sync input for serial interface TDMa
General-purpose I/O port C, bit 5
SMRxD1
PB24
TXADDR3
J18 I/O SMC1 receive data input
General-purpose I/O port B, nit 24
UTOPIA multi-PHY transmit address line 3
SMRxD2
L1CLKOA
PB20
PHSEL[0]
TXADDR0
L16 I/O SMC2 receive data input
Clock output from the serial interface TDMa
General-purpose I/O port B, bit 20
Most significant bit of PHY select bus
UTOPIA multi-PHY transmit address line 0
SMSYN1
SDACK1
PB23
TXADDR2
K17 I/O SMC1 external sync input
SDMA acknowledge
General-purpose I/O port B, bit 23
UTOPIA multi-PHY transmit address line 2
SMTxD1
PB25
RXADDR3
J16 I/O SMC1 transmit data output
General-purpose I/O port B, bit 25
UTOPIA multi-PHY receive address line 3
SMTxD2
L1CLKOB
PB21
PHSEL[1]
TXADDR1
K16 I/O SMC2 transmit data output
Clock output from the serial interface TDMb
General-purpose I/O port B, bit 21
Least significant bit of PHY select bus
UTOPIA multi-PHY transmit address line 1
SPICLK
PB30
C19 I/O SPI output clock in server mode or SPI input clock in client mode
General-purpose I/O port B, bit 30
SPIMOSI
PB29
E16 I/O SPI output data in server mode or SPI input data in client mode
General-purpose I/O port B, bit 29
SRESET
P2 I/O Soft Reset
TA C2 I/O Transfer Acknowledge
TCK
DSCK
H16 I/P Provides clock to scan chain logic
Provides clock to the development port logic
Table 8.10 MPC859T Port Assignments (Continued)
Pin Name Pin No. Type Function