46 Network Circuitry TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
Note The bits set to zero in the above table are obtained from the data
bus pull-downs. The external data bus bit designations are normal
numbering order as opposed to the PowerPC reverse numbering
order. (See “Terminology” on page 6.)
5.2.4 RISC External Bus Interface
The MPC has a single, unified bus structure for external data, code and
peripheral accesses, ie. it does not support the Harvard architecture
externally. The address and data buses are not multiplexed together, but
different address signals may be multiplexed onto the address pins for
interfacing to dynamic memory devices (see “Address Multiplexing and
Command Codes” on page 63)
MPC External Data
Bus
Note The numbering of the data bus lines on the schematic follows nor-
mal industry convention, ie. the lsb is D0, rather than the Pow-
erPC convention with D31 being the lsb. The transition from
PowerPC numbering order to normal numbering order occurs at
the MPC external pins, ie. MPC D31 is connected to data bus D0,
MPC D30 is connected to D1, and so on.
The MPC’s external data bus is 32 bits wide. Normally, the MPC attempts
to transfer data as 32-bit words, however, it can transfer data to/from 8-bit
Table 5.4 Boot Configuration Settings
External Data
Bus Pins Driven
High
MPC Configuration Register Bits
Operating Mode
Name Setting
EARB 0 External arbitration disabled
IIP 0 Initial interrupt prefix
BBE 0 Boot burst disabled
BDIS 0 Boot is enabled for device selected by CS0
d17 BPS 01 Boot port device size set to 16 bits
ISB 00 Base address on internal memory space is set
to 0x00000000
d21, d22 DGBGC 11 CPU debug status signals output on port
IB_B[0..7]
DBPC 00 BDM debug port functions enabled
d27 EBDF 01 Memory clock output is 1/2 internal clock
speed
CLES 0 Big Endian mode
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