TB9100 Reciter Service Manual Network Circuitry 51
© Tait Electronics Limited January 2006
On initial boot up the MPC must obtain its program code from the flash
EPROM, before the GPCM has been initialized by the MPC, to access that
flash EPROM. To overcome this problem, CS0
has a special default
configuration after reset: it is active for the entire external address space of
the MPC and inserts the maximum number of wait states per access.
Therefore, an EPROM connected to CS0
is selected, regardless of its
position in the memory map, and it can have an access time of up to 30 wait
states, ie. 480ns at a 62.5MHz memory clock. Once the MPC program is
loaded, it can reprogram the GPCM configuration for CS0
to assign the
flash EPROM’s normal address location and reduce the wait states to 5 clock
cycles for speedier access.
For CS0
the GPCM is programmed to assert the internal TA signal (see
“MPC Bus Cycles” on page 48) to terminate the bus cycle after the wait
states have expired. Software strobe output CS3
also utilizes the internal TA
signal.
However, the handling of CS2
differs; this is configured to be terminated by
the external TA
signal. Usually, a CS2 bus cycle is terminated by the external
signal, as applied by tri-state buffer U212. This buffer is controlled by the
HRDY signal from the DSP, signalling the completion of a HPI access cycle
(see “Host Port Interface (HPI)” on page 69). In the event that the HRDY
signal does not terminate the bus cycle within approximately 32us, the bus
cycle times out and is terminated by the bus monitor (see “Time Bases and
Watchdog” on page 42).
User-Programmable
Machines
UPMA is used for controlling accesses to, and generating the control signals
for, the SDRAM devices. As well as chip select CS1
, UPMA controls the
byte select lines, BS[0..3]
. The general-purpose memory control lines,
GPLA0
, GPLA1, GPLA2 and GPLA3, which correspond to the SDRAM
A10, RAS
, CAS, and WE inputs respectively (see “SDRAM Control
Inputs” on page 62), are also generated by UPMA. The UPM also controls
multiplexing of the row and column addresses (see “Address Multiplexing
and Command Codes” on page 63) onto the MPC’s lower order address
outputs.
The signal types and timing of the general-purpose memory control lines
are fully programmable, enabling the UPM to handle a wide variety of
memory and peripheral types. The configuration of these signals is
determined by a pattern stored in a small 64-word RAM in each UPM.
The RAM must be programmed with the appropriate data patterns by the
user program before any access can be made to memory controlled by a
UPM.
Each location in this RAM holds the data pattern to be sequentially output
on the general-purpose lines during a memory cycle. In response to a
memory cycle request, a counter is set to the appropriate location in RAM;
the RAM is subdivided into sections corresponding to the different types of
memory requests:
■ single word read cycle request
To Next Page
Loading...
Need help?
General
