TB9100 Reciter Service Manual Network Circuitry 53
© Tait Electronics Limited January 2006
Independently of the serial communications facilities provided by the CPM,
a fast ethernet controller (FEC) is provided for either 100Mbps (100BaseT)
or 10Mbps (10BaseT) ethernet. Both half-duplex and full-duplex modes are
supported.
The FEC implements only the media access controller (MAC) functions of
an ethernet interface. It requires external interface hardware to implement
the physical layer connection. The FEC connects to this ethernet physical
layer interface (PHY) device (see “Ethernet Physical Interface” on page 74)
using a media-independent interface (MII) bus (see “Media Independent
Interface (MII)” on page 76). It also supports a 7-wire interface to connect
to older 10Mbps physical interface devices, but this is not used in the ASIF.
For test purposes, the FEC can perform an internal loopback function
bypassing the PHY, or it can instruct the PHY to perform an external
loopback function.
For ethernet transmissions, the MPC will typically set up the data in a
transmit buffer location in external memory. The location of this buffer is
made known to the FEC via a transmit buffer descriptor (BD), also
describing the length of the data packet, its destination address and other
relevant settings. Thereafter, the FEC handles the necessary transmit
operations, eg. data frame formatting, preamble generation, data
transmission and appending CRC information, without further MPC
intervention. In the event of a transmit collision occurring, the FEC can
handle the transmit retries independently of the MPC.
Similarly for ethernet reception, the FEC handles preamble detection, frame
detection, address recognition, data reception and CRC checking. Received
data is placed in a memory buffer according to the receive buffer descriptor,
which is also records status information for the received frame. To minimize
loading on the MPC, the FEC employs several address filtering methods to
ignore ethernet frames that are not addressed to it.
Data transfers to/from the main memory buffers take place using DMA (see
“CPM Serial Direct Memory Access (SDMA)” on page 54). FIFOs within
the FEC allow the DMA to take place in bursts, minimizing the memory
bandwidth required.
5.2.6 Communications Processor
The CPM supports many varieties of serial interface protocols through
microcode executing from an internal ROM. It performs lower level control
of serial functions, taking much of the interface and protocol management
workload away from the main RISC CPU. A block diagram of the CPM is
shown in Figure 5.5. Reference should be made to Part V of the MPC866
user’s manual (reference 2) for a detailed description of the CPM’s
capabilities.
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