54 Network Circuitry TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
CPM Serial Direct
Memory Access
(SDMA)
To avoid the need for the MPC software to transfer large blocks of data to/
from the CPM, a DMA controller is implemented in the CPM. This DMA
controller can transfer to/from external memory and to/from the CPM’s
dual port RAM.
The DMA hardware supports two DMA channels, but the CPM software
expands this to 16 virtual DMA channels with dedicated channels assigned
to each serial device, eg. SCC, and SMC. A further two virtual DMA
channels are assigned for independent DMA to/from devices external to the
MPC. This function is not used in the ASIF.
Timers and Baud
Rate Generators
The CPM incorporates four 16-bit timers that may be concatenated to form
two 32-bit timers.
These timers can be used for general purpose timing when clocked from the
system clock, or they can be connected to an external signal via a timer input
pin. One timer is used to output a 25MHz clock, on TOUT1, for the
ethernet PHY. This clock is divided down from the MPC’s system clock.
When connected to an external signal, the timers can count events or mark
the occurrence of edges on those pins. One timer input, TIN3, connects to
Figure 5.5 Communications Processor Block Diagram
U-Bus
Serial Interface and Time-Slot Assigner
SCC1 SMC1 SMC2 SPI I
2
C
4 Baud Rate Generators
Parallel I/O Ports
4Timers
Interrupt Controller Bus Interface SDMA
8Kbyte
Dual-Port
RAM
Communications Processor
ROM
Peripheral Bus
Internal Bus
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