Tait TB9100 - Page 64

64 Network Circuitry TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
■ burst length = 4 (see “SDRAM Burst Cycles” on page 64)
■ burst write enabled
■ sequential address mode
■ CAS latency = 2
After a short time delay, the SDRAM is ready for normal operation.
SDRAM Read and
Write Cycles
The sequence of events for a single memory location write cycle is as
follows:
■ Set up row address and ACT command
■ Set WE line inactive (high), OE line to active (low)
■ Strobe in address and command with RAS going low
■ Set up column address and WRITE command
■ Strobe in address and command with CAS going low
■ Wait 2 clock cycles (CAS latency)
■ Latch data
■ Raise CAS
■ Set up PRE command
■ Raise RAS
■ Ready for next cycle
SDRAM Burst Cycles The MPC memory interface achieves high memory bandwidth by utilizing
the burst feature of SDRAMs. This allows multiple, adjacent address
locations to be read or written without inputting new addresses each time,
thus saving considerable time per access. During a burst access, an SDRAM
can read or write new data every clock cycle after the initial memory access.
The SDRAM burst size is set to four words to match the MPC RISC CPU
internal cache line refill size (see “Memory Caches and Memory Managers”
on page 40). Allowing for the setup time for the initial memory access, a
burst of four words can be fetched from memory in only 8 memory clock
cycles. With a memory clock of 62.5MHz, the SDRAMs can deliver
sufficient instruction code to the MPC for it to execute in excess of 30MIPs,
even when performing a cache refill.
SDRAM Refresh
Cycles
All dynamic memory devices use memory cells that indicate the state of a
bit by the level of charge stored on a minuscule capacitor. This charge can
leak away over a period of time so it is necessary to periodically top it up.
This is accomplished by executing a refresh cycle on each row in the
memory array. For the SDRAMs every row must be refreshed at least once
every 64ms.
Although all rows could be refreshed in one block every 64ms, to do so
would prevent the MPC from accessing its memory for an extended period.
It is preferable to perform refreshes on a distributed basis, ie. one row every