68 Network Circuitry TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
The actual multiplication ratio is set by programming an internal PLL
register; in the ASIF this will typically be set to 12, giving a DSP clock of
153.600MHz from the 12.800MHz reciter reference clock. An exact
(subject to reference clock tolerances) 2.048MHz CODEC clock may be
readily derived from this 153.6MHz clock with a divide-by-75 counter.
Optionally (see “Clock Oscillator” on page 81), the DSP reference clock
may be changed to the on-board 13.000MHz crystal oscillator. Multiplying
this reference clock by 11.5 gives a DSP clock of 149.500MHz. Dividing
this clock by 73 gives an approximate 2.048MHz (-27ppm error) CODEC
clock; this is sufficiently accurate for many applications.
Prior to the program being able to set up the PLL register, the DSP operates
in a PLL bypass mode where the DSP is operated directly from the reference
clock, or half the reference clock. This is determined by the CLKMD input,
which is tied low to select the 1:1 mode. Once the DSP program is up and
running, it programs the PLL registers, enables the PLL, and switches to
operating from the internal high-frequency clock.
Internal Memory No external memory is provided for the DSP, so all code and data has to be
stored in the on-chip memory. This consists of 160k of 16-bit half-words
made up of eight blocks, totalling 32k words, of dual-access RAM
(DARAM) and 32 blocks, totalling 128k half-words, of single-access RAM
(SARAM). Each type of internal memory can be accessed in a single clock
cycle, ie. zero wait states.
With DARAM, the DSP core can make two accesses (reads, writes or both)
to a single block of memory during a single clock cycle. DARAM enables
more efficient implementation of many DSP algorithms such as filtering,
buffering, etc. SARAM is limited to a single access (read or write) during a
clock cycle. Typically, SARAM is used for storing program code and
coefficient tables.
Since no external memory is used, most of the pins relating to the memory
interface (A[21..0], D31..0] et al.) are left unconnected. The exceptions are
the ready signal (ARDY) and bus hold (HOLD
); these are tied to their
inactive high states so that the DSP software does not hang indefinitely if it
erroneously attempts to access an external memory location. To prevent
excessive current drain caused by the data bus pins floating, these are held at
valid logic levels by internal “bus keeper” circuits. The current drain can
also be reduced by shutting down the EMIF circuitry.
Boot Loading As the DSP has no external program memory from which to start program
execution, it must start up in a boot loader mode to get program code from
an external source into its internal memory. The DSP incorporates a small
block (16k half-words) of ROM containing a boot loader program. See
reference 12 for details of the boot loader program operation.
By default, the DSP starts executing from the boot loader ROM when its
reset is released. One of the first operations of this boot loader program is to
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