TB9100 Reciter Service Manual Network Circuitry 67
© Tait Electronics Limited January 2006
The DSP incorporates a multi-channel DMA controller to facilitate rapid
data movement without requirement intervention from the DSP core.
This DMA controller can transfer data between the internal memory,
external memory and peripherals. It is also used as part of the host port
interface (see “Host Port Interface (HPI)” on page 69 for details).
The operation of the DMA controller is described in reference 10.
To facilitate program development, the DSP provides debugger access to its
internals through a modified JTAG test port brought out on connector J106.
This connector is not fitted to production boards. A full description of the
JTAG interface is outside the scope of this document; reference 22 should
be consulted for details.
Interrupts and Reset The DSP provides for six external interrupt inputs, although only one is
used for the ASIF. An external 1 PPS timing reference (see “1 PPS Input”
on page 73) is connected to IRQ0
, the highest priority maskable interrupt
input. This is used for providing the DSP with a server timing reference,
should it be required in simulcast networks. All other interrupt inputs are
tied to their inactive high state.
Interrupt facilities are also available between the DSP and MPC. The DSP
program can interrupt the MPC using the HINT
output. The MPC can
also interrupt the DSP using an internal interrupt register in the host port
interface (see “Host Port Interface (HPI)” on page 69).
The MPC controls the DSP reset line via a parallel output port (PA13) so
that it can force the DSP into reset to halt a runaway program, or to restart
the boot load process (see “Boot Loading” on page 68). If the MPC is reset,
output PA13 goes tri-state and resistor R200 pulls the DSP_RST
line low,
thus also resetting the DSP.
Peripherals Aside from the McBSP ports (see “Serial Interfaces” on page 71), the DSP
provides a limited set of peripherals: an 8-bit parallel I/O port, a single bit
output flag and two timer/counters. See the DSP peripheral reference guide
(reference 11) for details.
None of these peripherals are used in the ASIF application, but some of the
parallel port lines and the output flag are brought out to test points for
software debugging purposes. Three of the parallel I/O ports share pins with
the boot mode selection pins (see “Boot Loading” on page 68), but, after
reset is released, these can also be used as standard parallel I/O.
Clock Generation To achieve high performance, the DSP requires high frequency clock. To
minimize EMC generation this high-frequency clock is generated internally
to the DSP chip by multiplying up a relatively low-frequency reference
clock input using an internal phase-locked loop (PLL). The input reference
clock (CLKIN) can be multiplied by various ratios ranging from 0.25 to 31
with the proviso that the final PLL operating frequency must lie in the range
80MHz to 160MHz.
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