TB9100 Reciter Service Manual Network Circuitry 75
© Tait Electronics Limited January 2006
The internal logic of U700 runs from a +2.5V supply, which is generated
from the +3.3V supply by an internal voltage regulator. Its output,
VCC25OUT, is fed back to power the internal logic, as well as supplying
the line transformers.
5.6.2 Ethernet PHY Configuration
The PHY is configurable for various operating modes and speeds, by
software control of internal mode register settings, or by sensing the state of
various pins on power up.
Software configuration of the internal registers in PHY is accomplished over
the Serial Management Interface (SMI) from the MAC. Data is transferred
on a bi-directional data line (MDIO) and latched on the rising edge of the
clock (MDC) supplied from the MAC. Refer to the AC101L data sheet
(reference 17) for a listing of the configuration registers.
As an alternative to SMI configuration, some of the PHY register settings
can be made through strapping external pins; the state of these pins is sensed
on the rising edge of RST and latched into the internal registers. These
mode setting pins have internal pullups, so will read high if left
unconnected.
Since the MDIO line is bi-directional, the PHY status can also be read back
via the SMI. Refer to the AC101L data sheet (reference 17) for a listing of
the status registers. To indicate a change of status the PHY can output an
interrupt request on its INTR
pin; this goes to a general-purpose interrupt
input, IRQ4
, on the MPC.
One further hardware pin, PDOWN
, is used to put the PHY into a low-
power standby mode when taken low. This pin is driven by a general-
purpose output, PB15, from the MPC.
Table 5.13 PHY Configuration Settings
Pin Reset State Mode Selection
LED0/Burnin# High Burnin disabled
LED1/SPD100 High 100Mbps enabled
LED2/Duplex High Full duplex enabled
LED3/ANEN Low Auto-negotiate mode disabled
CRS/Repeater Low Repeater mode disabled
To Next Page
Loading...
Need help?
General
