76 Network Circuitry TB9100 Reciter Service Manual
© Tait Electronics Limited January 2006
5.6.3 Ethernet PHY Clocking
Timing of the internal operations of the ethernet PHY requires an external
25.000MHz clock source. This is provided from a timer output, TOUT1,
of the MPC to the XI input of the PHY. The timer divides down from the
MPC clock, hence this must be an exact multiple of 25 MHz. Inter nal to the
PHY, the 25MHz clock is multiplied by a PLL to 125MHz, to form the line
symbol bit rate clock: 100Mbps ethernet encodes the line data, so that 5 bits
are transmitted for every 4 input bits, hence the line bit rate is 125MHz.
The PHY outputs a 25MHz clock (for 100Mbps) or 2.5MHz (for 10Mbps)
on the TXCLK for timing the data transfers over the MII (see “Media
Independent Interface (MII)” on page 76). For received data, the PHY
regenerates a clock from the incoming data stream and divides this by four
to output a 25MHz or 2.5MHz clock on the RXCLK output.
5.6.4 Media Independent Interface (MII)
The PHY connects to the MPC FEC via a Media Independent Interface
(MII). This is an 18 line bus (including the SMI lines) for connecting
multiple PHYs to a MAC, although in the ASIF’s case, only one PHY is
used. Data transfer to/from the FEC occurs over separate receive and
transmit buses, each four bits wide, and are clocked by RXCLK and
TXCLK respectively, supplied from the PHY.
On reception of a valid signal on the receive line inputs, the carrier sense
(CRS) line goes active. Shortly after, Receive Data Valid (RXDV) goes
high, indicating the presence of valid data on the MII receive data bus,
RXD[3..0]. Data on this bus is latched into the FEC on the rising edge of
the RXCLK clock. Should an error be detected in the received signal, the
Receive Error (RXER) line goes high; this is also latched on the rising edge
of RXCLK.
On transmission, the FEC places data on the transmit data bus, TXD[3..0],
and asserts TXEN high, to indicate valid data on the bus. The data is latched
into the PHY on the rising edge of TXCLK and is then formatted for
transmission to line via the transmit data outputs. If, for any reason, the FEC
needs to abort a transmission, it asserts the transmit error (TXER) line; this
causes the PHY to transmit an invalid signal, which will be detected by the
remote receiver.
With ethernet, there is a potential for two devices to transmit to the network
simultaneously, causing a data collision. While a transmission is in progress,
the receiver section monitors the network for a collision condition. Should
one occur, the Collision (COL) output is set high, indicating to the FEC
that it has to retry the transmission later.
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