Technics SL-P202A - Internal Connection of Fl

@ INTERNAL CONNECTION OF FL
reyee
eS
e
O
|
e
Grid
connection
diagram
CXKS8I6M
16K RAM IC 302)
14G 13G
CONTROL e Pin connection table
siRqQ. TL HFD Si/ O00DS STAT TRON OMUTE Oscls MLD/MCLK / EMPH
RD osc2 MDATA
MNISS4PJE -2
SYSTEM CONTROL
1
1C501 enti 00~7 RAM O~10/0E /WE SRDATA |
ANe371 =>
DATA SLICE & PLL 1C301
1C801 > Len
ara MN6625 BCLK |
MN647)
ADJ. DIGITAL SIGNAL PROCESSING LINE OUT
vRSOt LRCLK DIGITAL FILTER
&
—
384fs
D/A
CONVERTER
{>
Rech
+5V
pa oe See H
~ “e Fe/Pe BLKCK/ MEMP
STAT TRON DMUTE CLDCK/SUBQ SMCK RST RSTB XI,X2
| '
IC 404 xeoU 0801,802,854,855 t
TRACK LOSS DET.
| >| DE-EMPHASIS
5 i] | n
{ 0851~853
MUTING |
'
=] 80-3
USE 4 0431,432
_—--]
peep
seh
ope
a
MOTOR
DRIVE
ae ey FIF IN|, NININ| felon |; [Ule5[t4fisin iN (N{N|t2{ti]10] 9) 8|7]}6]5 | 4
2/21P]° © PIPIP GIGIGIGIP|PIP|P|GIGIG/GIGIG|G/G|G
TRAYSW POL. SPOW3 SKATE CMDO~3 RESET CLK RECV SEND ACK DATAO~3
SKATE Dive
'
IC 403 1C601
MNISSIPJF -1
PERIOD DET & RST
SPEED CONTROL
MNIS283PEY
FL DRIVE
e Anode connection table
$0-8
L
a
zo
g>
go
gz 2S
‘
1
‘
() '
| |
| '
| OPERATION CIRCUIT | LOADING UNIT |
4 4 44 REMOTE
—| off] Be,
“i RSLOOOIF
aot 2 Fn a
GENERATOR
es eee ee
l. MCLK : Data clock for MDATA
for LAG network SUBQ : Sub-code Q data Note) Rages
rack jumping. CLDCK : Data frame clock (7.35KHz) Sue Be
laser supply and BLKCK : Sub-code Q data block clock (75 Hz) *——> Audio signal. | No. | index | — |
RST ==: Reset command (Active Low) Petey litik
TRON : Tracking servo ON command (Active Low)
1 devided by four. EC : Spindle motor drive signal
PC : Spindle motor ON command (Active Low)
signal (Active High) SMCK : System clock (4.2336MHz)
OE : Read out enable
WE : Write enable
4, 2336MHz) LRCK : L/R data discrimination clock (88.2KHz)
rison signal SRDATA : Serial data output (MSB first)
CRC etc. SCK : Serial bit clock (2.82MHz)
MEMP : Deemphasis command (Active High)
de control data
— 19 — — 20 —