Theory of Operation—2465B/2467B Service
The last dot-data bit DD7 is the EOCH (end of charac-
ter) bit and, when LO, indicates that the last dot of the
character is addressed. It is used to reset the Dot Counter
(via U2855B) and enables the Character Counter to be
incremented (via U2855A) after the last dot of a character
has been displayed.
Two servicing jumpers, J401 and J402, have been pro-
vided to disable the Character ROM and force the DD7 bit
( EOCH ) LO. In certain instances, these two conditions
may be useful when troubleshooting the Readout circuitry.
To prevent damage to the ROM output circuitry, J402
should only be installed after J401 is installed (to disable
the ROM).
Dot Counter
The Dot Counter consists of two four-bit counters (both
within U2870), OR-gate U2835A, inverter U2980D, and
inverting input AND-gate U2855B. It sequences through a
block of addresses containing dot-position data for a
selected character. The Dot Counter is incremented when
a dot is finished (via Inverter U2980D) by the GETDOT
sig-
nal from the Dot Cycle Generator.
The counter increments through the block of dot-
position data until the last byte of the block is encountered
(last dot). This last data byte has the EOCH (end of char-
acter) bit (DD7) set LO. The dot is positioned and
displayed in the normal manner, but when the GETDOT
signal occurs for the next dot display cycle, the EOCH bit
is latched into U2905 and generates the EOCH1 (end of
character, delayed one dot) signal at U2905 pin 18. With
EOCH and EOCH1 both LO, the HI reset pulse produced
at pin 4 of NOR-gate U2855B resets the counter and,
except for space characters, the EOCH bit returns HI. As
the reset is removed from the Dot Counter, it is reenabled
for display of the next character. For space characters, the
EOCH bit will be detected as a LO when the first dot is
read from the Character ROM, and the Character Counter
will advance to the next character on the next rising edge
of GETDOT
Counter U2870 and OR-gate U2835A enable characters
of more than 16 dots to be displayed. Since most of the
readout characters are small, using 16 dots or less,
efficient data storage is achieved by storing the dot-
position data as 16 consecutive bytes. For displaying
these smaller characters, the least significant four bits
from U2870 are sufficient to address the 16 possible dot-
position bytes.
When larger characters (up to 32 dots) are to be
displayed,
an additional bit of counter data must be used
to address the ROM. This fifth bit comes from U2870 pin
3 and is ORed by U2835A with bit CDO from the Charac-
ter RAM. The block address for these larger characters
always has bit CDO set LO, so the counter bit from U2870
pin 3 is in control of the ROM address line at pin 4 of
U2930.
When displaying these larger characters, the dot
count goes beyond 16 dots before the EOCH bit is set LO.
On the seventeenth character, the fifth counter bit (pin 3 of
U2870) will go HI to address the next 16-byte block of
character data in ROM U2930. The lower four bits of the
DOT Counter then sequence through this additional block
in the normal manner until the EOCH bit is encountered,
resetting the counter.
Horizontal DAC
The Horizontal DAC generates the voltages used to
horizontally position dots of the readout display on the crt.
Five data bits (CAO through CA4) from the Character
Counter stage position a character to the correct column
in the display (32 possible columns across the crt), while
three data bits from Character ROM U2930 (DDO through
DD2) horizontally position the dots within the eight-by-
sixteen character matrix (see Figure 3-6).
The eight bits of position data are written to the per-
manently enabled DAC each time a new dot is requested
by the Dot Cycle Generator. The GETDOT signal applied
to pin 11 (Chip Select) enables the DAC to be written into,
and the falling edge of the 5-MHz clock applied to pin 12
(Write) writes the data at the eight DAC input pins into an
internal latch. The voltage at the DAC output pin changes
to reflect the data present in the latch.
Vertical Character DAC
The function of Vertical Character DAC U2905 is similar
to that of the Horizontal DAC just described. It is responsi-
ble for vertically positioning each character dot on the crt.
The Vertical DAC circuit is made up of seven,
D-type
flip-
flops (contained within U2905) and an accompanying resis-
tor weighting network. The outputs of the flip-flops source
different amounts of current to a summing node through a
resistor weighting network.
The seven data bits are latched into U2905 on the
ris-
ing edge of the GETDOT signal. Two bits of character
address data (CA5 and CA7) from the Character Counter
switches the vertical display position between the four
readout display lines. When the display is to be in the bot-
tom line, bit CA5 is set LO. With CA5 LO, zener diode
VR2925 is biased off and a small current is sourced to the
summing node via R2925. Vertical position above this
reference is determined by dot data bits DD3 through
DD6.
When the top line is to be displayed, the CA5 bit is
set HI, biasing VR2925 on. A larger current is now
sourced into the summing node via R2925 and enough
voltage is developed across R2926 to move the display to
3-30
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