Theory of Operation—2465B/2467B Service
output LO at the beginning of the A Sweep. This enables
the B Sweep to run immediately at the start of the A
Sweep and is used for calibration purposes and for
options.
The capacitive load (part of the etched-circuit board) at
the RDA (retrace delay adjust) input (U700 pin 4) is used
to delay the retrace of the sweep until the Z-Axis drive is
fully turned off in response to the SGAZ gate going HI.
This delay prevents any part of the retrace from being
seen.
B Sweep
Operation of B Sweep hybrid U900 is similar to that
just described for the A Sweep with the following excep-
tions:
the THO input (and thus sweep enabling) is
con-
trolled by the A Sweep hybrid or the measurement PAL
and not the Display Sequencer (see the preceding A
Sweep description). The timing capacitor select output,
TCS,
is not used, and only three timing capacitors are
selectable (two on the B Sweep hybrid at CTO and CT1
and one externally at CT2).
Calibrator
The Calibrator circuit, composed of Q550, U165B,
U550A, B, C, and D, and associated components,
gen-
erates a square wave output of precise amplitude and
fre-
quency characteristics. The CALIBRATOR signal provided
at the front-panel output connector is useful for adjusting
probe compensation and verifying VOLTS/DIV, SEC/DIV,
and At (delta time) calibration. Output frequency is
con-
trolled by the Display Sequencer and is set to display five
cycles across the ten crt graticule divisions at sweep
speed settings from 100 ns per division to 100 ms per
divi-
sion.
This feature allows quick and easy verification of the
sweep rates. The Calibrator circuitry is essentially a volt-
age regulator that is alternately switched on and off, pro-
ducing the square-wave output signal.
When the timing signal (CT) from the Display
Sequencer to the base of U550D is LO, U550C (configured
as a diode) is forward biased, shunting bias current away
from Q550, keeping it turned off. When transistor Q550 is
off, the front-panel CAL OUT connector is pulled to ground
potential through R558, setting the lower limit of the
CALI-
BRATOR output signal.
As the CAL signal goes from LO to HI, the emitter of
U550D is pulled HI to reverse bias U550C. Bias current for
Q550 is established, and the transistor is turned on. The
voltage at the emitter of Q550 rises to a level of +2.4
volts,
determined by the voltage regulator composed of
U165B,
U550A, U550B, and associated components. This
regulated level is applied to the front-panel CALIBRATOR
connector through a voltage-divider network composed of
R557 and R558. This produces an output voltage of 400
mV with an effective output impedance of 50 ft.
Since the frequency of the CALIBRATOR signal is
con-
trolled by the same divider chain that controls operation of
the vertical chopping rate, the intentional 200-ns shift
added to the chop signal at the end of some sweeps (to
desynchronize the chopping rate from the sweep rate)
shows up on the CALIBRATOR signal as an irregular-
width pulse. This shift is not apparent when viewing the
CALIBRATOR signal on the instrument providing the
sig-
nal (since the skew occurs during sweep-retrace time), but
it should be taken into account when using the CALIBRA-
TOR signal with other instrumentation. The skew can be
eliminated from the signal by setting the instrument
TRIGGER MODE to SGL SEQ (to shut off the sweeps).
PARAMETRIC MEASUREMENTS
The VOLTS Parametric Measurement is made using
the same methods and circuitry that is used in the Auto
Level trigger mode to find the peak voltages. The accuracy
of the VOLTS measurement is based on the accuracy of
the trigger level and the DC balance of the instrument.
All of the time-based Parametric Measurements use the
A and B Sweep gates and delay gates as the basis for the
measurements.The measurement PAL, U975, controls the
signal flow while in the Parametric mode. The measure-
ment flip-flop, U980B, reports the state of a variety of
con-
ditions to the SLIC through the SGB line. The SLIC data is
read by the processor system and used to compute the
desired measurement.
VERTICAL CHANNEL SWITCH AND
OUTPUT AMPLIFIERS
The Vertical Channel Switch (diagram 6) selects the
sig-
nal source for vertical deflection of the crt beam. The Vert-
ical,
Horizontal, and Z-Axis output amplifiers provide the
signal amplification necessary to drive the crt.
Vertical Channel Switch
The Vertical Channel Switch consists of hybrid Channel
Switch U400, that selects one of the vertical signals for
application to the Vertical Output Amplifier, and a com-
bined switch/amplifier circuit that converts the single-ended
readout vertical signal into a differential signal for applica-
tion to the Channel Switch.
Channel selection is controlled by the Display
Sequencer VS1 through VS4 signals applied to the vertical
channel selection pins (pin 24, pin 25, pin 13, and pin 14
respectively). (See Table 3-3 for the Vertical Display Selec-
tion.) When a vertical select line is LO, the associated
input signal pins are connected to the differential output
(
+
OUT,
pin 11 and -OUT, pin 3). The CH 5 input signal
3a-23
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