Theory of Operation—2465B/2467B Service
+
5
V through the resistor divider composed of R2928 and
R2929. A larger current is now sourced into the summing
node via R2925 and enough voltage is developed across
R2926 to move the display to the top row of the crt. The
CA7 bit is used to offset the top and bottom readout
display lines to form the center two readout display lines.
As before, the individual dots are then positioned above
this reference level by dot data bits DD3 through DD6.
Mode Select Logic and Analog Channel Switch
The Mode Select Logic circuitry is composed of analog
switches U2800 and U2805, buffers U2820B and C, gates
U2810A, B, C, and D, U2900B and C, and part of U2905.
It controls the readout display mode by selecting which
deflection signals should drive the Horizontal and Vertical
Deflection Amplifiers during a readout display. Five display
modes are decoded by the Mode Select Logic: character
display, vertical cursor 0, vertical cursor 1, horizontal cur-
sor 0, and horizontal cursor 1.
For normal character displays, cursor select bit CA6 on
U2800 pin 1 is LO. This LO signal passes through analog
switch U2800 and is latched into U2905 when the
GETDOT request from the Dot Cycle Generator goes HI.
This latched LO selects the character display mode by
forcing the outputs of U2900B and C and U2810A and B
HI.
The HI outputs of U2900B and C applied to the select
input pins of analog switch U2805 cause the Horizontal
DAC output signal applied to U2805 pin 11 to be routed to
the Horizontal Amplifier (diagram 6) via buffer U2820B.
The same HI logic levels cause NOR-gates U2810C and D
to produce a LO at their outputs. This causes analog
switch U2800 to route the Vertical DAC output signal
applied to pin 12 to the Vertical Output Amplifier (also
diagram 6) via buffer U2820A.
For cursor displays, cursor select bit CA6 goes HI. This
HI is routed through analog switch U2800 and latched into
U2905 when GETDOT next goes HI. This produces a HI at
U2905 pin 16, enabling the Mode Select Logic to decode
output bits DD3, DD4, and DD5 (from U2905) to determine
which of the four possible cursor modes is selected (see
Table 3-6). Once one of the cursor modes is entered, ana-
log switch U2800 routes a fixed HI from pin 5, pin 2, or pin
4 to U2905 to keep the Mode Select Logic enabled. Char-
acter display mode is reentered only when return-to-
character-mode data is decoded (DD4 and DD5 both LO).
When that occurs, U2800 routes the CA6 bit to U2905
and,
if the bit is LO, the cursor display mode is halted.
CURSOR DEVELOPMENT. Cursors are displayed in
short sections, alternating between both vertical positions
(for the delta voltage cursors) or both horizontal positions
(for the delta time cursors). When displaying delta voltage
cursors, the CURSOR 0 level is routed to the Vertical
Amplifier by analog switch U2800. This level determines
the vertical position of one of the voltage cursors.
Horizontal-positioning voltages for one segment of the
cursor are routed from Horizontal DAC through analog
switch U2805 and buffer U2820B to horizontally position
each of the dots making up the cursor segment. DLY REF
1 is then used to vertically position the second cursor, and
the Horizontal DAC positions each of the dots for that
cursor segment. The cycle is repeated until all segments of
both cursors are displayed.
Table 3-6
Readout Display Mode Selection
Control Bits
CA6
(Cursor Select)
L
H
H
H
H
H
DD5
X
a
L
L
H
H
L
DD4
X
H
H
L
L
L
DD3
X
L
H
L
H
X
Mode
Selected
Character Display
Vert Cursor 1
Horiz Cursor 1
Vert Cursor 0
Horiz Cursor 0
Horizontal
Signal
Horiz DAC
Horiz DAC
DLY REF1
Horiz DAC
CURSOR 0
Vertical
Signal
Vert DAC
DLY REF1
Horiz DAC
CURSOR 0
Horiz DAC
Return to character display Mode
State doesn't matter.
3a-31
To Next Page
Loading...
