Tektronix 2467B

Theory of Operation—2465B/2467B Service
When chopping between vertical channels, the Display
Sequencer adds a 200-ns skew at the end of some
sweeps to desynchronize the chop frequency from the
sweep speed (to prevent the sweep from locking onto the
chop frequency). Due to this, the Calibrator signal has an
irregular pulse repetition characteristic between sweeps.
This will not be apparent when observing the Calibrator
signal on the instrument crt since the skew is synchro-
nized to the sweep, but may be observed when the Cali-
brator output signal is used with other instrumentation.
The skew can be eliminated by setting the instrument to
SGL SEQ Mode (to shut off the sweeps).
Holdoff Circuitry
The holdoff circuit, used to delay the start of a sweep
until all circuits have recovered from the previous sweep,
is made up of U165C, Q154, Q155, and associated com-
ponents. Operational Amplifier U165C and capacitor C180
form a sample-and-hold buffer used to set the charging
current for holdoff-ramp integrating capacitor C171 (C660
for the 2467B). A control voltage from digital-to-analog
converter (DAC) U2201 (diagram 2) via multiplexer U170
(diagram 4) is stored on C180. The stored voltage level
sets the base voltage for both Q154 and Q155 via
amplifier U165C. Transistors Q154 and Q155 form a
current-mirror with nearly equal collector currents. Transis-
tor Q154 is a current-to-voltage converter that provides
negative feedback to U165C, setting loop gain. Transistor
Q155 acts as a constant-current source that charges
integrating capacitor C171 (C660 for the 2467B), produc-
ing a linear holdoff ramp.
A comparator circuit in U650 detects when the ramp
crosses a predefined threshold voltage (approximately +3
V). When the threshold is reached, pin 10 of U650 (HRR)
goes LO and the integrating capacitor is discharged. At
that same time, an internal counter that keeps track of the
holdoff ramp cycles is incremented. The ramps continue to
be generated and reset until the holdoff ramp counter has
counted the number of ramp cycles defined by the sweep-
rate-dependent holdoff data field stored in the Display
Sequencer control register. At all sweep speeds except 5
ns per division, the count is at least two holdoff ramp
cycles. The front-panel variable HOLDOFF control affects
holdoff time by varying the HOLDOFF control voltage to
U165C (from the DAC), changing the charging rate of
integrating capacitor C171 (C660 for the 2467B).
When holdoff time requirements are met (determined by
the number of ramps counted), the Display Sequencer sets
the THO (trigger holdoff) signal LO. This enables both the
A Sweep hybrid (U700) and the A Trigger circuitry in U500.
The Trigger circuit begins monitoring the selected trigger
source line and, when a triggering event is detected that
meets the triggering requirements defined by the stored
control data, initiates the A Sweep and sets the TSA
(trigger status, A Sweep) line to Display Sequencer U650
LO (indicating that the A Sweep has been triggered).
As the A Sweep circuit (U700) responds to the trigger,
it sets the SGA (sweep gate A) line LO (via U980A) indi-
cating that an A Sweep is in progress. After the sweep
has run to completion, U700 sets the SGA line HI signaling
the end of sweep. The Display Sequencer then sets the
THO line HI, resetting A/B Trigger hybrid U500 and A
Sweep hybrid U700 in preparation for the next sweep.
HOLDOFF BOARD (2467B ONLY). Holdoff ensures that
the sweep generator fully recovers between successive
sweeps. It inhibits the sweep and trigger for a specific
holdoff time after each sweep. The Display Sequencer
(U650) sets THO (Trigger HOIdoff, pin 13) high, which
resets and inhibits both the A trigger and the A sweep.
Then, after the holdoff time elapses, THO is set low,
enabling the A trigger and A sweep to respond to the next
trigger event. The Display Sequencer and external circuitry
form a holdoff timer.
The holdoff timer operates only while SGA (not Sweep
Gate A, at the base of Q159) is high. Holdoff time is pro-
portional to a number of holdoff-timer cycles, counted by
the Display Sequencer, according to the selected sweep
speed. A capacitance and a charging current determine
the duration of each holdoff-timer cycle. The HOLDOFF
control varies the current to adjust the cycle duration in
the range from about 1 us to about 15 ^s.
The circuit comprising operational amplifier U165C and
transistors Q154 and Q155 generates the charging current
for the holdoff timing capacitors C660, C169, C173, and
C174. When the voltage on C174 rises above +5 V, com-
parator U168B drives the HRR terminal of the Display
Sequencer U650 high, through emitter follower Q158,
diode U1169H, diode-connected Q161, and R177. C172
also charges to about +4 V. The Display Sequencer then
drives HRR back to ground and counts one holdoff-timer
cycle. Stored charge in the base-collector junction of
diode-connected Q161 supplies the high current needed to
rapidly switch HRR from low to high and R177 limits the
current required from U650 to drive HRR back from high
to low. When HRR is driven below the voltage on C172,
comparator U168A discharges C660, C169, C173, and
C174.
When both the output of comparator U168A is low and
SGA is high, Q157, R179, R178, and U169F form a
current mirror. This establishes a discharge current for
C169, proportional to the charging current from the collec-
tor of Q155, and normalizes the operation of the circuit for
all settings of the variable HOLDOFF control.
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