Tektronix 7834

Theory of Operation-7$34
Storage Mode Switching
E rase
1 A HI logic level is +5 volts
except for NS
(+15
V) and VP (+15 V) which are +15 volts
in the HI state .
This stage,
comprised of 02642, 02644, and S2404, pro-
vides do control signals
for the Storage System . Table 3-6
lists the logic levels of the
control signals for the five posi-
tions of the Storage Mode
Switch, S2404 .
This stage
develops the Erase and Erase pulses, which ini-
tiate the storage erase cycle . It consists of
three sections :
(1) monostable multivibrator,
U2562A, (2) input logic for
the stage, 02514, 02526,
02528 and 02542, (3) oscillator
02538, 02532 and 02536
.
Each
time pin 2 of U2562A goes HI and pin 1 is
LO,
an
Erase pulse is generated . However, if pin 1 of U2562A
is
H I (see Save Mode Switching) no Erase pulse can be
gene-
rated by the signal on pin 2 . The width of the erase pulse
(determined by R2562 and C2562) is approximately
100 milliseconds .
When the front-panel ERASE push button
(S2538) is
pressed, the NS (+15 V) logic level is connected to
R2516 .
In all storage modes the NS
(+15
V) signal is at +15
volts .
Therefore, current from the +15 volt
supply passes through
C2521 to momentarily turn on
02526
.
When 02526 con-
ducts, 02542 turns off, and a
HI
is
applied to pin 2 of
Q2562A to generate an Erase pulse .
Whenever a position on the Storage
Mode Switch (S2404) is
selected, or the
REDUCED SCAN switch (S2558) is pressed,
the switching transitions coupled
through C2523 and 02526
or C2528 and 02528 initiate
an Erase pulse .
Transistors, 02532, 02536, and 02538, comprise a
variable
frequency low-speed oscillator controlled
by the front-panel
AUTO ERASE control
. The PUT (programmable unijunc-
tion transistor) 02538,
is connected as a relaxation oscilla-
tor with
C2534
as
the timing capacitor . Current to charge
3-
7 2
TABLE 3-6
Storage
Mode Switch Output Logic Levels
Transfer and
Multi
C2534 is
provided by a variable-current source,
02536,
controlled by the AUTO ERASE viewtime
control R2537 .
Each time 02538 turns on to discharge
C2534, a voltage
spike is applied to R2540 which turns 02542
off and trig-
gers an Erase pulse .
Transistor 02532, when on, inhibits the
operation of the
oscillator by holding C2534 discharged
. When P2531 is set
for Periodic operation, the
X+Y logic signal (see Main
Timing) turns
02532 on for approximately 1 .4 seconds
after the
start of each Erase pulse, and then allows
C2534
to resume char ging . When P2531 is set
for After Sweep
operation the Multi signal (see Transfer and
Multi) turns
02532 on at the beginning of the Erase
pulse and holds it
on until the end of the next
sweep . When the AUTO
ERASE switch (S2537) is set to
the OFF Position 02532 is
biased on to inhibit the
Auto Erase function .
When the Save
signal (see Save Mode Switching), connected
to R2539, goes
HI the auto erase oscillator is inhibited ;
however, 02538 is
allowed to turn on immediately after
the Save signal returns LO,
providing C2534 is sufficiently
charged .
This stage develops
the Tsfr and Tsfr pulses which initiate
the
transfer operation in the fast storage modes, the
Multi
and Njulti signals
which indicate whether a display has been
stored since the
last erase cycle occurred, and the SwF++Tsfr
signal
which indicates whether a waveform is being written
or the transfer
operation is occurring .
When the Storage Sweep Gate is H I, current flows into
R2584 turning off 02586 and causing a HI level to appear
at its collector . Also, HI level applied to
the REMOTE
STORAGE GATE INPUT turns off
02586 to provide a HI
level at its collector . U2588A
inverts the HI and applies it
to pin 8 of
U2588C . If the Storage Lockout signal (see
Storage Lockout)
at
pin 9 of U2588C is LO, the signal is
inverted to
provide a replica of the Storage Sweep Gate or
the Remote Storage Gate signals at pin 10 of U2588C .
Storage
Display Mode
NS NS NS (+15 V)' VP (+15 V) 1
FAST
NON-STORE
HI LO LO LO
HI HI
BISTABLE LO HI HI LO
HI HI
VAR PERSIST
LO HI HI
HI HI
FAST BISTABLE
LO HI HI
HI LO
FAST VAR
PERSIST LO ~ HI HI
HI LO LO