Tektronix 7834

The four gates of U2592, along with C2592, comprise a
monostable multivibrator which generates a short positive
pulse whenever the output of U2588C goes LO . This end-
of-sweep
circuit operates as follows : Assume that the out-
put of U2588C is LO and that the output of U2592D is H I .
Then, the outputs of U2592A and U2592C will be LO .
When the output of U2588C goes HI, the flip-flop comp-
rised of U2592A and U2592D changes states . The output
of U2592C, however, still remains LO . When the output of
U2588C returns LO, the output of U2592C immediately
goes HI since both of its inputs are now LO .
Both inputs to U2592B are also LO so its output switches
to the HI state . Capacitor C2592 loads the output of
U2592B to provide a delay of approximately 100 nano-
seconds in the LO to
H I
transition . At the end of this delay
the flip-flop, U2592A and U2592D, switches back to its
initial state and the output of U2592C returns
LO .
The 100
nanosecond end-of-sweep pulse
from
U2592C
provides a trigger to
U2592A,
to generate a 100-millisecond
wide Tsfr pulse at the end of the sweep whenever the Fast
signal is LO . The pulse also clocks U2682B so that the Multi
signal goes HI at the end of the first sweep after an erase
pulse occurs ; the Erase pulse clears this
flip-flop
.
The end-
of-sweep pulse is also coupled to U2608B in the Readout
Control stage (see Readout Control)
.
U2608C generates the
Swp+Tsfr
signal through a combination
of inputs
from
U2588C
and
U2594A .
Save Mode Switching
This stage, consisting of 02626, 02632 and U2588D,
develops the Save signal which enters the Storage System
into the Save
mode of operation
. Pressing the front-panel
SAVE push
button
switch, S2624,
or
grounding
the rear-
panel REMOTE
SAVE
INPUT -,
J2625, will initiate the Save
signal by turning off 02626 which in turn saturates 02632 .
However, if one of the storage modes is not selected,
NS (+15 V) connected to the collector of 02626 will be at
zero volts and 02632 will remain off to prevent the Save
signal from occurring .
When 02632 saturates to produce the Save signal, the
SAVE front-panel light, DS2624, turns on and a LO is ap-
plied to pin 12 o f U2588D . The Save output signal goes H I
only if the Multi signal at pin 11 is LO . That is, the Save
signal can only be produced if a sweep has occurred since
the last Erase pulse . This action performs the Auto Save
function .
Main Timing
This
stage develops the
W, X, Y,
and
Z
signals, their comp-
lements, the X + Y signal, and the X-Multi signal . These
signals control the
major sequence of voltages applied to
Theory of Operation-7834
the crt during the Erase and
Multi-Trace cycles
.
This stage
also accepts input information from the
time-base unit(s)
via the A or B Single Sweep Logic line and the Storage
Single Sweep Reset line, and generates the Storage Single
Sweep Reset signal to reset the time-base unit(s) during any
Erase or Multi-Trace cycle .
The X signal, developed by U2684A, is a positive pulse with
a duration of 150 milliseconds to
4
seconds .
The X signal
goes HI when 02674 turns on pulling pin 1 of
U2684A LO .
This occurs under one of the three following conditions
:
(1) When an Erase pulse occurs, (2) in the Fast Storage
modes when the MULTI TRACE
DLY
control
S2616 is in
the detent (-) position, or the time-base unit(s)
is in the
Single Sweep mode and a Multi-Trace cycle
is externally
initiated, and (3) in the Fast Storage
modes when S2616 is
out of the detent, the time-base
unit(s)
is in
a repetitive
sweep mode, and the Multi-Trace cycle
automatically recurs .
The input path for condition number 1 above is
through
R2673 when Erase goes
HI .
The input path
for condition
number 2 is through CR2664, C2668, and 02668
when the
Storage Single Sweep Reset line is pulled LO (time base
unit(s) single sweep reset button is pushed or the
REMOTE
RESET
input is grounded) . Transistor 02658
must be off
so
W
(explained later) must
be LO insuring that any pre-
viously initiated Erase or
Multi-Trace cycle has been ter-
minated . The input path for condition
number
3
is through
C2671 when Tsfr returns
HI
after the
transfer operation .
Transistor 02654 must be off so the time-base unit(s) must
be in a repetitive sweep mode and the MULTI TRACE DLY
control must be out of the detent .
The width of the X pulse is determined by 02612, 02678,
and U2552B . When the X pulse is triggered by an Erase
pulse, Multi (emitter of 02612) is
LO
and
Multi is HI .
Diodes CR2610 and CR2615 are reverse-biased and charging
current for the timing capacitor C2676 passes through
CR2614, R2613, and R2676 . In this condition, the X pulse
lasts approximately 900 milliseconds . When the Multi-Trace
cycle is externally initiated, Multi is HI and the output of
U2552B is LO (A or B Single Sweep Logic line is HI or
S2616 is in the (-) detent position), so 02612 is on . Diode
CR2614 is reverse-biased so charging current for C2676
passes through 02612, CR2610, and R2676 . Under this
condition, the X pulse duration is approximately 150 milli-
seconds . When the Multi-Trace cycle automatically recurs,
the output of U2552B is LO . If Multi is HI, timing current
passes through R2616, the MULTI TRACE DLY control,
and the pulse width is variable from approximately 150
milliseconds to 4 seconds . If Multi is LO, timing is as in
condition number 1 . Transistor 02678 is a current stage
which insures adequate drive for pin 15 of U2684A under
any of the above timing conditions . The connection at pin 3
of U2684A inhibits the X pulse when NS is LO . Resistors
R2652, R2653, R2655, and R2657 inhibit the X pulse
when SAVE or FAST are Hl .
3- 7 3