Tektronix 7834

Theory of
Operation--7834
At the
end
of
the X pulse (if the A or B Single Sweep Logic
line is HI) current from the rising edge of
X
is coupled
through R2662 and C2663 into the base of
02664 produc-
ing a negative reset pulse on the Storage
Single Sweep
Reset line .
The Y signal, generated by U2684B, is a positive
pulse
which occurs at the end of the X pulse . The
Y pulse is
triggered by 3( coupled through C2684 to
pin 10 of U2684 .
Transistor 02694 inhibits the generation of
the Y pulse
whenever X, Save or Fast is H I . Components R2685
and
C2685
set the width of the Y pulse to approximately 400
milliseconds .
The W signal is generated by U2682A
. W goes H I at the
beginning of the Y pulse and is
normally reset LO at the
end of the Tsfr pulse by the coupling
of Tsfr through
C2683 . However, if X, Save, or Fast go
HI, 02694 will also
reset W LO . The Z signal, generated
by U2594B, is a posi-
tive pulse which occurs at
the end
of
the Y pulse . Compo-
nents R2696 and C2696
set the width of the Z pulse at
approximately
100 milliseconds . The X +Y signal is formed
directly by U2556A,
and the X-Multi signal is formed
directly
by U2588A .
Clock
This stage generates the Clock
and 10-kilohertz Ramp sig-
nals for use by the rest of
the storage system . The PUT
02772, and components
R2770, C2770 and R2779 form a
relaxation oscillator
operating at a frequency of approxi-
mately 100 hertz
. Components 02774, R2774, R2775,
R2779 and C2774 form a
similar oscillator operating at a
frequency of approximately 10
kilohertz . Both oscillators
have a common gate-biasing
resistor, R2779, that provides
synchronous oscillations
.
To
illustrate, consider that
C2770 is initially discharged
and 02772 is nonconducting .
The time constant of C2774 and
R2774 is much shorter
than the time constant of C2770 and
R2770 . Therefore,
02774 oscillates at approximately
10 kilohertz while the
anode voltage of 02772 slowly
rises . Each time 02774
turns on, gate current is
drawn from R2779 causing the
gates of 02772 and
02774
to
drop approximately 350
millivolts . Thus, the anode firing
voltage for 02772 is lower
when 02774 is on . This causes
02772
to
synchronize with
02774 .
When 02772 is
on,
it
draws sufficient gate current to tem-
porarily stop
the oscillation of 02774 and turn 02784 on
for approximately 50
microseconds . This action generates
the Clock pulses .
The amplitude of the Clock pulses is
approximately 10 volts with a -5 volt base line, set by
02788, R2785, R2786, and R2787 . The
10-kilohertz Ramp
signal is taken directly from
the anode of 02774 .
Persistence
Pulse Generator
This stage, comprised of 02502, 02506, 02508, and
U2565A generates a Clock frequency pulse train, at the
3- 7 4
collector of 02508, with pulse
width continuously variable
by the PERSISTENCE control
. These pulses control the
persistence of the display
in both of the Variable Persist-
ence modes . Operation of
the stage is as follows .
Transistors 02502 and
02506 are connected as a compara-
tor . The PERSISTENCE
control determines the voltage
level applied to the base of
02502 . When the CLOCK pulse
goes HI, 02508
switches
on
to discharge C2507 to about
-5 volts .
When the PERSISTENCE control is adjusted away
from the MAX position,
02502 turns on and 02506 turns
off . At the same time, the output
of U2565A goes LO to
hold the collector of 02506
LO . When the Clock pulse
returns LO, a positive
pulse begins at the collector of
02506 . Current
through R2507 begins to charge C2507,
raising the
base voltage of 02506 . When the base voltage
of
02506
exceeds
that
of 02502, transistor 02506 turns on
and the collector of
02506 again goes LO . When the
PERSISTENCE controls is set to the MIN position,
the
pulse
width is approximately 1 .8 milliseconds
. If the
PERSISTENCE control is set to MAX, 02506
never turns
off and no positive pulses are produced at
the collector
of 02506 .
Save Intensity
Pulse Generator
This stage,
comprised
of
02572, 02576, 02578, and
U2565C generates a Clock frequency pulse train at
the
collector
of 02576 with pulse width continuously
variable
by the SAVE INTENSITY control . These pulses
are applied
directly to the Flood Gun Cathode Driver stage to
adjust
the display intensity in the Save mode . With the
SAVE
INTENSITY control set to MIN, pulses are not
produced ;
with the SAVE INTENSITY control set to MAX, the pulse
width is
approximately 10 milliseconds . Operation of this
stage is identical to the previously described Persistence
Pulse Generator Stage .
Prep
This stage, comprised of U2556B, C, and D and U2552C,
develops the Prep signal . This signal directs the Storage
Mesh Logic Decoder to switch the Storage Mesh to the Prep
Level when operating in the Variable Persistence storage
modes (see Fig's . 3-49 and 3-51) . The inputs to
this
stage
are from the Persistence Pulse Generator, Save Mode
Switch-
ing, Transfer and Multi, and Main Timing stages .
Fast Prep
This stage, comprised of U2562B and U2552A,
generates
the Fast Prep signal . The Fast Prep signal is
used by the
Storage Mesh Decoder
and Fast Mesh Decoder stages in the
transfer (FAST BISTABLE or FAST VAR PERSIST)
modes
.
U2562B produces a clock frequency pulse train, the
width of
the pulses (set by R2565 and C2565) is approxi-
mately 1 .8 microseconds . When W is LO, these pulses are
inverted by U2552A to form the Fast Prep signal
. When
-W177MM is LO, and W is LO, the Fast Prep
signal remains
H I . When W is H I, the Fast Prep signal stays LO .