Tektronix 7834 - Page 78

Theory of Operation-7834
ALT MODE
INHIBIT  __
(VERT)
VERTICAL
ALTERNATE
COMMAND
VERTICAL
ALTERNATE----W I
COMMAND
4
7
8
U4412
6
ALTERNATE
7 9-
DRIVE
Clock Generator
Part of integrated
circuit U4320 along with
the external
components
shown in Figure 3-16A
make up the Clock
Generator stage
. R 1, Q1, 02, and
Q3 represent an equiva-
lent
circuit within U4320 . This
circuit along with
discrete
components
C4314-114312-134313-114314
compose a
two
megahertz
free-running oscillator
that provides a timing
(Clock)
signal used to synchronize
the vertical, horizontal,
and
plug-in chopping modes .
(1195-14)
1988-39
I

This stage
operates as follows :
Assume that Q2 is
conduct-
ing and 01 is off . The collector
current of Q2 produces
a
Figure 3-14 . Input and output
pins for Plug-In Binary IC
(U4412) .

voltage drop across R 1 to turn
off 01 . This negative
level at
the collector of Q2 is also
connected to pin 14 through
Q3
(A) U4412
3- 2 2
INPUT
(D = HAS NO EFFECT
IN THIS CASE .
'ACTUATED BY
NEGATIVE-GOING EDGE
.
OUTPUT
CHANNEL 1 DISPLAYED )
ALL VERTICAL
MODES EXCEPT ALT PRO-
VIDE SWEEP-SLAVING
FOR NON-DELAYED
CHANNEL
2 DISPLAYED

DUAL-SWEEP
OPERATION .
n+1 = IF OUTPUT
IS LO PRIOR TO LO' IT GOES
HI, AND VICE VERSA .
(B)

2
REPETITION
RATE ONE-HALF VERTICAL
ALTERNATE COMMAND
RATE .
ALTERNATE
DRIVE
Figure 3-15 . (A)
Logic diagram for
Plug-In Binary stage ; (B) Table of input/output
combinations .
(1195-15) 1988-40