Tektronix 7834 - Page 79

(see waveforms in
Figure 3-16B at time TO) . Since there is
no current through
01, C4314 begins to charge towards
---15 volts through R4312-R4313
. The emitter of 01 goes
negative as C4314 charges, until
it reaches a level about 0 .6
volts more negative than the level
at its base . Then 01 is
forward biased and its emitter rapidly rises
positive (see
Time T1 on waveforms)
.
Since C4314 cannot
change its
charge
instantaneously, the sudden change in voltage
at the
emitter of Q1 also pulls
the emitter of Q2 positive to
reverse-bias it . With Q2 reverse
biased, its collector rises
positive to produce a positive output
level at pin 14 .
Now, conditions are reversed . Since Q2
is reverse biased,
there is no current through it . Therefore,
C4314 can begin
to discharge through R4314 . The emitter level
of 02 fol-
lows
the discharge of C4314, until it reaches a level of
about
0 .6 volt more negative than its base . Then
Q2 is forward
biased and its collector drops negative
to reverse-bias Q1 .
The
level at pin 14 also drops negative
to complete the
cycle .
Once again, C4314 begins to charge through
R4312-
R4313
to start the second cycle .
Two
outputs are provided from this oscillator . The
Delay
Ramp signal
from the junction of R4312-R4313 is
con-
nected
to the Vertical Chopped Blanking
stage
.
This signal
To
T
1
(1195-16) 1988-41
Figure
3-16 . (A) Diagram of clock generator stage ; (B) Idealized
waveforms for clock generator stage .
Vertical Chopped Blanking
Theory of Operation-7834
has the same
waveshape as shown by the waveform at pin 13 ;
its slope is
determined by the divider ratio between R4312-
R4313 . A
wide pulse train output is provided at pin 14 .
The frequency of this pulse
train is determined by the
overall RC relationship
between C4314-R4312-R4313-
R4314 and its duty cycle is determined by
the ratio of
R4312 and R4313 to R4314 .
The pulse train
at
pin
14 is connected to pin 16 through
C4315 . Capacitor C4315, along
with the internal resistance
of U4320, differentiates the pulse
train at pin 14 to produce
a narrow negative-going pulse
coincident with the falling
edge of the pulse train
(positive-going pulse coincident with
rising edge has no effect
on circuit operation)
.
This negative-
going pulse is connected to pin
15 through an inverter-
shaper that is also part of U4320A . The
output at pin 15 is
a positive-going clock pulse with
a
repetition
rate of about
two megahertz .
The Vertical Chopped Blanking stage is
made up of the
remainder of U4320 . This stage determines
if Vertical
Chopped Blanking pulses are required,
based upon the oper-
ating mode of the vertical system
or the plug-in units (dual-
trace units only) . Vertical
Chopped Blanking pulses are
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