Tektronix 7834 - Page 81

Chop Counter
CLOCK, PIN 15 U215A
DELAY RAMP, PIN 10 U215B
VERTICAL CHOPPED BLANKING,
PIN 4 U215B
T
O
The
Delay Ramp signal from the Clock Generator stage
determines the repetition rate and pulse width of the Verti-
cal Chopped Blanking pulses . The Delay Ramp applied to
pin 10 starts to go negative from a level of about +1 .1 volts
coincident with the leading edge of the Clock pulse (see
waveforms in Fig .
3-18) .
This results in a HI quiescent
condition for the Vertical Chopped Blanking pulse . The
slope of the negative-going Delay Ramp is determined by
the Clock Generator stage . As it reaches a level slightly
negative from ground, the Vertical Chopped Blanking pulse
output level changes to the LO state and remains LO until
the
Delay
Ramp
goes HI again .
Notice the delay
between the
leading
edge of the Clock
pulse generated by U4320A, and the leading edge of the
Vertical Chopped Blanking pulses . The amount of delay
between the leading edges of these pulses is determined
by
the Delay Ramp applied
to
pin 10 . This delay is necessary
due to the delay line in the vertical deflection system .
Otherwise, the trace blanking resulting from the Vertical
Chopped Blanking pulse would not coincide with the
switching between the displayed traces . The duty cycle of
the wide pulse train produced in the Clock Generator stage
determines the pulse width
of
the Vertical Chopped Blank-
ing pulses (see Clock Generator Description for more
information) .
The Chop Counter stage U4340 produces the Vertical Chop-
ping Signal, the Plug-In Chop Drive, and the Horizontal
Chopped Blanking signal . The Clock pulse produced by the
Clock Generator stage provides the timing signal for this
stage . The functions of the input and output pins for the
Chop Counter IC, U4340, are identified in Figure 3-19A .
Idealized waveforms showing the timing relationship be-
tween the input and output signals for this stage are shown
in Figure 3-1913
.
DELAY
Figure 3-18 . Idealized waveforms for Vertical Chopped Blanking stage .
Theory of
Operation--7834
(1195-18) 1988-43
The repetition rate of the output signals from this stage
is
determined by the setting of the HORIZONTAL MODE
switch . When the HORIZONTAL MODE switch is set to
any position except CHOP, the repetition rate of the Verti
cal Chopping Signal output at pin 1 is one megahertz
(one-
half Clock rate) . This determines the
switching between the
LEFT
and
RIGHT VERT units when the VERTICAL
MODE switch is set
to CHOP
.
At
the same time, the repeti-
tion rate of the Plug-In Chop Drive at pin 8 is 0 .5 megahertz
(one-fourth Clock rate) . This provides a chopping signal for
switching between the two channels of dual-trace vertical
units . The relationship between these output signals and the
Clock input is shown by the waveforms in Figure 3-19B
during the time between TO and T1 . During this time, the
level
at pin
4 remains HI .
When the HORIZONTAL MODE switch is set to CHOP, the
basic repetition rate of the Vertical Chopping Signal and
the Plug-In Chop Drive is altered . For example, if the
HORIZONTAL MODE switch is changed to the CHOP
position at time T - 1 (see Fig . 3-19B), a HI level is applied to
pin 6 . This stage continues to produce outputs at pins 1 and
8 in the normal manner until both outputs are at their HI
level . (See time T2 ; this condition only occurs once every
fifth Clock pulse and only when the HORIZONTAL MODE
switch is set to CHOP .) When both of these outputs are at
their HI level, the next Clock pulse switches both outputs
LO, and at the same time switches the Horizontal Chopped
Blanking to the LO level .
This change at time T2 does not appear at pin 4 immediate-
ly, due to a delay network in the circuit . The delay is neces-
sary to make the Horizontal Chopped Blanking coincide
with the Vertical Chopped Blanking produced by U4320
and
the switching between the displayed signals . (Compare
bottom two waveforms of Fig . 3-1913 ; also see Vertical
Chopped
Blanking for further information .) After the delay
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