Tektronix RSA5106B Technical Reference

Specifications
Digital IQ Out
put Timing
All I/Q signals output from the FPGA are synchronous to the 200 MHz
Acquisition Data clock, received over the high-speed LVDS interface from the
digital inte
rface board; all signals are registered at the FPGA pins. (See Table 69.)
The IQ clock is generated so as to have a 50% duty cycle (±5%), regardless of
clock rate. The IQ clock is set so that it has the rising edge in the center of the
settled data and DAV signals, which allows near symmetric setup and hold time.
Table 68: EXT_IQ_DAV Duty cycle versus Span
Span EXT_IQ_CL
K frequency (MHz)
EXT_IQ_DA
V duty cycle (%)
60 MHz 200 50.0
40 MHz 50 100.0
20 MHz 50 50.0
10 MHz 50 25.0
5 MHz 50 12.5
2 MHz 50 6.250
1 MHz 50 3.125
500 kHz 50 1.5625
200 kH
z
50 0.781
25
100 kHz 50 0.39063
50 kHz 50 0.19531
20 kH
z
50 0.09
7656
10 kHz 50 0.048828
5 kHz 50 0.024414
2kH
z
50 0.0
06104
1 kHz 50 0.003052
500 kHz 50 0.001526
20
0kHz
50 0.
000763
100 kHz 50 0.000381
The rising edge of EXT_IQ_CLK is aligned to be in the center of the settled
E
XT_I[15:0], EXT_Q[15:0], and EXT_IQ_DAV signals.
68 RSA5100B Series Technical Reference

Tektronix RSA5106B Specifications

General

Brand	Tektronix
Model	RSA5106B
Category	Measuring Instruments
Language	English