Specifications
Warranted Specifications
Characteristi
c
Description
Input parameters with probes
Threshold Accuracy
TLA5000B, TLA7N4 ±100 mV
TLA7ACx, TLA7Bxx ±(35 m V + 1% of the threshold voltage setting)
Channel-to-channel skew
TLA7N4
≤ 1.6 ns maximum (When merged, add 0.5 ns for the slave module.)
TLA5000B ≤ ±150 ps maximum
≤ 75 ps (Typical)
TLA7ACx
≤400 ps maximum
When merged, add the following for slave modules: 0.0 ns when data is acquired
on the slav
e modules through local clocks 125 ps when data is acquired on
the slave modules by the master modules’ clock and merge deskew has been
performed. 375 ps when data is acquired on the slave modules by the master
module’s
clock and merge deskew has NOT been performed.
TLA7Bxx
±40 ps ma
ximum, module only (for P6800 and P6900 series probes, add ±60 ps)
±20 ps (Typical), module only
Asynchr
onous sampling
Sampling period
1
The fas
test sampling rate for each logic analyzer goes to 50 ms in a 1–2–5
sequence
TLA7N4
4 ns, 250 MS, all channels
2 ns, 500 MS half channels
TLA7ACx, TLA5000B 2 ns, 500 MS, all channels
1ns,
1000 MS, half channels
500 ps 2000 MS, quarter channels
TLA7
Bxx
1.25 ns, 800 MS, all channels
625 ps, 1600 MS, all channels
313
ps, 3200 MS, half channels
157 ps, 6400 MS, quarter channels
Minimum recognizable word
2
(across all channels)
Channel-to-channel skew + sample uncertainty
Example for a P6860 Probe and a 1.25 ns sample period: 160 ps + 1.25 ns =
1.
45 ns
S
ynchronous sampling
Setup and hold window size (data and qualifiers)
TLA7N4
Maximum window size = Maximum channel-to-channel skew + (2 x sample
uncertainty) + 4 ns. Maximum setup time = User interface setup time + 0.8 ns.
Maximumholdtime=Userinterfaceholdtime+2ns
Maximum setup time for slave module of a merged pair = User interface setup
time + 0.8 ns
Maximum hold time for slave module of a merged pair = User interface hold time
+0.7ns
44 TLA Q uick Start User M anual
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