LE910Cx Hardware Design Guide
1VV0301298 Rev.40 Page 84 of 149 2023-03-16
Not Subject to NDA
Figure 21: Auxiliary PCM Timing
Parameter Comments
Min Typ Max Unit
t(auxsync) AUX_PCM__SYNC cycle time - 125 - µs
t(auxsynca) AUX_PCM_SYNC asserted time 62.4 62.5 - µs
t(auxsyncd) AUX_PCM_SYNC de-asserted time 62.4 62.5 - µs
t(auxclk) AUX_PCM_CLK cycle time - 7.8 - µs
t(auxclkh) AUX_PCM_CLK high time 3.8 3.9 - µs
t(auxclkl) AUX_PCM_CLK low time 3.8 3.9 - µs
t(suauxsync)
AUX_PCM_SYNC setup time to
AUX_PCM_CLK rising
1.95 - - ns
t(hauxsync)
PCM_DIN hold time after
AUX_PCM_CLK rising
1.95 - - ns
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