Texas Instruments BQ76922EVM - Figure 6-10. Schematic Diagram Fets

R29
VSS
PGND
VSS
Red
D3
FUSE
10k
R53
10k
R46
10M
R39
10M
R32
Q9
10M
R38
0.1uF
C25
0.1uF
C24
5.1k
R54
0.1uF
C34
5.1k
R45
20k
R52
0.1uF
C33
0.1uF
C26
0.1uF
C27
100
R28
1.0k
R33
1
3.9k
R36
10M
R31
4
7,8
1,2,3
5,6,
Q7
Q4 Q5
5.1k
R49
1
2
3
F1
SFK-3030
Q10
BQ771807DPJR
VDD
1
V5
2
V4
3
V3
4
V2
5
V1
6
VSS
7
OUT
8
PAD
9
U4
1.0k
R42
0.1uF
C31
0.1uF
C29
0.1uF
C28
1.0k
R35
5.1k
R47
5.1k
R48
10k
R50
4
7,8
1,2,3
5,6,
Q8
1.0k
R30
10M
R40
16V
D4
1.0k
R26
10M
R27
0.1uF
C21
0.1uF
C20
4
7,8
1,2,3
5,6,
Q3
Q2
FBAT
10k
R55
10k
R56
TP26 TP27 TP28 TP29
TP24
TP23
TP36TP35
0
R34
4
7,8
1,2,3
5,6,
Q6
0
R44
51
R43
40V
D7
16V
D6
16V
D5
5P
4P
3P
2P
1P
1.0k
R41
1.0k
R37
TP31 TP32
TP30
TP25
TP22
TP33 TP34
100V
D8
PACK-
PACK+
PGND
PACK-
PACK+
E4
0.1uF
C32
0.1uF
C30
1
2
3
4
J9
PGND
1
2
J8
0.1uF
C23
0.1uF
C22
E3
CPACK+
CPACK+
PACK
LD
DSG
PDSGPCHGCHG
FUSE
PCHG PDSG
PACK LD
Output
22V 10A max
D3 and R35 are not required in design, but used to simulate fuse blown condition.
1
CD
NT2
CPACK+
PACK+
TP37
PGND
100V
D12
100V
D11
100V
D10
VSS
100V
D9
1.0k
R51
Cgate
PCgate
PDgate
Dgate
Figure 6-10. Schematic Diagram FETs
BQ76922EVM Circuit Module Physical Construction www.ti.com
30 BQ76922EVM Evaluation Module SLVU957A – SEPTEMBER 2019 – REVISED NOVEMBER 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated